Multilayer Perceptron Neural Network Architecture using VHDL with Combinational Logic Sigmoid Function

S. P. Joy Vasantha Rani, P. Kanagasabapathy
{"title":"Multilayer Perceptron Neural Network Architecture using VHDL with Combinational Logic Sigmoid Function","authors":"S. P. Joy Vasantha Rani, P. Kanagasabapathy","doi":"10.1109/ICSCN.2007.350771","DOIUrl":null,"url":null,"abstract":"This paper presents the hardware realization of fast and flexible feed forward neural network which is capable of dealing with fixed point arithmetic operations using VHDL with minimum number of CLB slices and good speed of performance. The hardware architecture of neural network with two input, one output and three hidden neurons occupies only 44% of CLB slices. An efficient and fast carry look-ahead adder and Booth multiplier are the essential building blocks of the processing elements to perform parallel computation in the neural network. The activation function has been carried out based on piecewise linear approximation only with combinational logic circuits","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Conference on Signal Processing, Communications and Networking","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSCN.2007.350771","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

This paper presents the hardware realization of fast and flexible feed forward neural network which is capable of dealing with fixed point arithmetic operations using VHDL with minimum number of CLB slices and good speed of performance. The hardware architecture of neural network with two input, one output and three hidden neurons occupies only 44% of CLB slices. An efficient and fast carry look-ahead adder and Booth multiplier are the essential building blocks of the processing elements to perform parallel computation in the neural network. The activation function has been carried out based on piecewise linear approximation only with combinational logic circuits
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
基于组合逻辑Sigmoid函数的VHDL多层感知器神经网络结构
本文提出了一种基于VHDL的快速灵活的前馈神经网络的硬件实现方法,该神经网络具有处理定点算术运算的能力,并且具有最少的CLB切片数和良好的性能速度。两输入一输出、三个隐藏神经元的神经网络硬件结构仅占CLB切片的44%。高效、快速的进位前瞻加法器和布斯乘法器是实现神经网络并行计算的基本组成部分。激活函数仅在组合逻辑电路中基于分段线性逼近实现
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Multilayer Perceptron Neural Network Architecture using VHDL with Combinational Logic Sigmoid Function A Service Time Error Based Scheduling Algorithm for a Computational Grid ASIC Architecture for Implementing Blackman Windowing for Real Time Spectral Analysis FPGA Implementation of Parallel Pipelined Multiplier Less FFT Architecture Based System-On-Chip Design Targetting Multimedia Applications Modified Conservative Staircase Scheme for Video Services
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1