Optimised completion detection circuits for null convention logic pipelines

Abstract

Null Convention Logic is a Quasi Delay Insensitive asynchronous design technique which requires special completion detection circuits that span the width of the data path to control the timing and ensure correct operation. These circuits occupy a large area on the chip and their propagation delay greatly affects the throughput of the system. In this paper, we propose a few improved techniques for implementing these completion detection circuits. Instead of designing the circuit using template-based NCL threshold gates, we simplify and merge the gates and route complementary Data and Null values as appropriate to ensure correct operation. Optimizing transistor sizes to achieve equal propagation delays in both the Data-Null and Null-Data transitions results in an area saving of over 30% and an energy saving of about 50% compared to conventional completion circuits. A further modification to the THxx gate circuit is shown that merges the Hold and Drive sections of the circuit to create a smaller, more balanced gate with better performance.