Pub Date : 2017-10-01DOI: 10.1109/PRIMEASIA.2017.8280361
A. M. Basuwaqi, M. Khir, A. Y. Ahmed, A. Rabih, M. U. Mian, J. Dennis
This research work focuses on performance analysis of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device which has been designed and fabricated for humidity sensing purpose. The sensor was designed following the standard 0.35 μm CMOS technology. The device is working using electrothermal principle. Alternative current is supplied to its embedded heater which results in moving the thin film. The sensing principle is based on the change in amplitude of the device due to adsorption or absorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changing the mass of the device. Although the sensor showed a response to the increase and decrease of humidity, its output signal was nonlinear. To investigate the factors that lead to nonlinear output, the sensor has to be investigated before it is deposited to determine the base output of the sensor. In this paper, the device was tested at low frequency range of 1 Hz to 5 Hz, and the applied voltage was in range of 1 Vrms to 4 Vrms. Wheatstone quarter and half bridge configurations were used to carry out the experimental process. It is observed that the best linear output of the device was achieved at 3 Vrms and 3.5 Vrms. Furthermore, the linearity has improved using Wheatstone half bridge configuration by 6.6% and 11.14% at 3 Vrms and at 3.5 Vrms, respectively.
{"title":"Effects of frequency and voltage on the output of CMOS-MEMS device","authors":"A. M. Basuwaqi, M. Khir, A. Y. Ahmed, A. Rabih, M. U. Mian, J. Dennis","doi":"10.1109/PRIMEASIA.2017.8280361","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280361","url":null,"abstract":"This research work focuses on performance analysis of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device which has been designed and fabricated for humidity sensing purpose. The sensor was designed following the standard 0.35 μm CMOS technology. The device is working using electrothermal principle. Alternative current is supplied to its embedded heater which results in moving the thin film. The sensing principle is based on the change in amplitude of the device due to adsorption or absorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changing the mass of the device. Although the sensor showed a response to the increase and decrease of humidity, its output signal was nonlinear. To investigate the factors that lead to nonlinear output, the sensor has to be investigated before it is deposited to determine the base output of the sensor. In this paper, the device was tested at low frequency range of 1 Hz to 5 Hz, and the applied voltage was in range of 1 Vrms to 4 Vrms. Wheatstone quarter and half bridge configurations were used to carry out the experimental process. It is observed that the best linear output of the device was achieved at 3 Vrms and 3.5 Vrms. Furthermore, the linearity has improved using Wheatstone half bridge configuration by 6.6% and 11.14% at 3 Vrms and at 3.5 Vrms, respectively.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116663438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/PRIMEASIA.2017.8280382
Suhaidi bin Shafie, N. A. M. Yunus, Ong Wei Chiek, W. C. Yew, I. Halin
This project is aimed to develop the layout for the analog signal path of a 4 transistor pixel CMOS image sensor using EDA tools in standard 0.13μm Silterra fabrication technology. The sub-circuit blocks that define the analog input-output path consists of the 320×240 pixel array, 320 column parallel correlated double sampling circuits, an output buffer amplifier and all associated bias circuitry. Each pixel size has a dimension of 10μm × 10μm. The pixel's frame rate is targeted to be 120 frames per second (fps) working in a QVGA picture format (320× 240 pixels). From simulation, the illumination range of 0.01 lux to 0.25 lux has been tested and shows only a 2.8% error from the ideal output linearity.
{"title":"Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology","authors":"Suhaidi bin Shafie, N. A. M. Yunus, Ong Wei Chiek, W. C. Yew, I. Halin","doi":"10.1109/PRIMEASIA.2017.8280382","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280382","url":null,"abstract":"This project is aimed to develop the layout for the analog signal path of a 4 transistor pixel CMOS image sensor using EDA tools in standard 0.13μm Silterra fabrication technology. The sub-circuit blocks that define the analog input-output path consists of the 320×240 pixel array, 320 column parallel correlated double sampling circuits, an output buffer amplifier and all associated bias circuitry. Each pixel size has a dimension of 10μm × 10μm. The pixel's frame rate is targeted to be 120 frames per second (fps) working in a QVGA picture format (320× 240 pixels). From simulation, the illumination range of 0.01 lux to 0.25 lux has been tested and shows only a 2.8% error from the ideal output linearity.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125067728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/PRIMEASIA.2017.8280349
Hamzah N. Al-Rawi, W. Ismail
Due to its low cost and availability, magnetic sensors nowadays are often incorporated into security systems to detect or localize threats. This paper, with the help of a correlated pre-published work, describes preliminary steps to ensure reliable results that could help in reducing inaccuracies/ errors in case of considering a security system that detects Magnetic IEDs employing AMR-based magnetic field sensors.
{"title":"Enhancing magnetic IEDs detection method utilizes an AMR-based magnetic field sensor","authors":"Hamzah N. Al-Rawi, W. Ismail","doi":"10.1109/PRIMEASIA.2017.8280349","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280349","url":null,"abstract":"Due to its low cost and availability, magnetic sensors nowadays are often incorporated into security systems to detect or localize threats. This paper, with the help of a correlated pre-published work, describes preliminary steps to ensure reliable results that could help in reducing inaccuracies/ errors in case of considering a security system that detects Magnetic IEDs employing AMR-based magnetic field sensors.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122995950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/PRIMEASIA.2017.8280378
T. Zulkifli, A. Marzuki, S. Murad
This paper presents an ultra-wideband 3.1–4.9 GHz low noise amplifier (LNA) employing a sixth-order bandpass Chebyshev filter. The LNA has been designed using Silterra 0.18 μm CMOS technology at 1.8 V power supply. The simulation shows that the LNA attains a power gain of 14.1 dB with an input reflection coefficient less than −10 dB in frequency range of interest, a noise figure of 4.29 dB at 3.8 GHz, gain flatness of ±0.25 dB, a 1 dB compression point of −17.67 dBm, −6.90 dBm for IIP3 and power dissipation of 4.5 mW excluding the buffer stage.
{"title":"UWB CMOS low noise amplifier for mode 1","authors":"T. Zulkifli, A. Marzuki, S. Murad","doi":"10.1109/PRIMEASIA.2017.8280378","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280378","url":null,"abstract":"This paper presents an ultra-wideband 3.1–4.9 GHz low noise amplifier (LNA) employing a sixth-order bandpass Chebyshev filter. The LNA has been designed using Silterra 0.18 μm CMOS technology at 1.8 V power supply. The simulation shows that the LNA attains a power gain of 14.1 dB with an input reflection coefficient less than −10 dB in frequency range of interest, a noise figure of 4.29 dB at 3.8 GHz, gain flatness of ±0.25 dB, a 1 dB compression point of −17.67 dBm, −6.90 dBm for IIP3 and power dissipation of 4.5 mW excluding the buffer stage.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131957955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/PRIMEASIA.2017.8280352
B. I. Abidin, Yeoh Keat Hoe, Y. T. Khok, Ong Duu Sheng
The generation of THz signal by quasi-ballistic electron reflection in a monolayer graphene is demonstrated by using ensemble Monte Carlo method. The device consists of a monolayer graphene acts as a channel confined between two thick oxide layer. The device is powered by an alternating constant bias to simulate the electronic transport in the channel. A gradual increase in the radiation amplitude is observed with decreasing channel length and increase in applied bias. Our simulations shows that quasi-ballistic electron reflection in graphene is capable of producing THz radiation up to 4 THz for channel length of 500 nm.
{"title":"THz radiation in graphene based on quasi-ballistic electron reflection","authors":"B. I. Abidin, Yeoh Keat Hoe, Y. T. Khok, Ong Duu Sheng","doi":"10.1109/PRIMEASIA.2017.8280352","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280352","url":null,"abstract":"The generation of THz signal by quasi-ballistic electron reflection in a monolayer graphene is demonstrated by using ensemble Monte Carlo method. The device consists of a monolayer graphene acts as a channel confined between two thick oxide layer. The device is powered by an alternating constant bias to simulate the electronic transport in the channel. A gradual increase in the radiation amplitude is observed with decreasing channel length and increase in applied bias. Our simulations shows that quasi-ballistic electron reflection in graphene is capable of producing THz radiation up to 4 THz for channel length of 500 nm.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116410470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/PRIMEASIA.2017.8280380
W. C. Yew, S. Shafie, I. Halin, R. Sidek
Image clarity is an important criterion in digital imaging. However, typical rolling shutter type complementary metal-oxide semiconductor (CMOS) image sensors with frame rate of 30fps which is used for relatively slow speed image capture suffers from image blur phenomena when capturing the fast-moving objects. Therefore, an integrating chip control circuit is needed for a high frame rate shift registers structure readout control circuit to overcome the image blur phenomena suffered by rolling shutter readout scheme. In this paper, a timing generator acts as the control circuit for 120fps CMOS image sensors on 0.13μm CMOS technology is developed. The design is modeled and analyzed using ModelSim for FPGA verification and post layout validation is successfully demonstrated with Synopsys EDA tool. The on-chip timing generator design block results in total power consumption of 4.0733μW and total design area of 61.64 χ 60.64 μm2.
{"title":"Timing generator for 120fps CMOS image sensors on 0.13 μm CMOS technology","authors":"W. C. Yew, S. Shafie, I. Halin, R. Sidek","doi":"10.1109/PRIMEASIA.2017.8280380","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280380","url":null,"abstract":"Image clarity is an important criterion in digital imaging. However, typical rolling shutter type complementary metal-oxide semiconductor (CMOS) image sensors with frame rate of 30fps which is used for relatively slow speed image capture suffers from image blur phenomena when capturing the fast-moving objects. Therefore, an integrating chip control circuit is needed for a high frame rate shift registers structure readout control circuit to overcome the image blur phenomena suffered by rolling shutter readout scheme. In this paper, a timing generator acts as the control circuit for 120fps CMOS image sensors on 0.13μm CMOS technology is developed. The design is modeled and analyzed using ModelSim for FPGA verification and post layout validation is successfully demonstrated with Synopsys EDA tool. The on-chip timing generator design block results in total power consumption of 4.0733μW and total design area of 61.64 χ 60.64 μm2.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121997044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/PRIMEASIA.2017.8280381
C. Hong, Noor Faezah Ismail, N. A. M. Yunus, D. Ahmad
This paper emphasizes the optimization of piezoresistive pressure sensor. The proposed design is to implement inner diaphragm to increase the sensitivity of the sensor. Comparison between the original design and proposed design is made. The adjustment and performance of the proposed design are also discussed.
{"title":"Sensitivity of piezoresistive pressure sensor with inner diaphragm","authors":"C. Hong, Noor Faezah Ismail, N. A. M. Yunus, D. Ahmad","doi":"10.1109/PRIMEASIA.2017.8280381","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280381","url":null,"abstract":"This paper emphasizes the optimization of piezoresistive pressure sensor. The proposed design is to implement inner diaphragm to increase the sensitivity of the sensor. Comparison between the original design and proposed design is made. The adjustment and performance of the proposed design are also discussed.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128750916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/PRIMEASIA.2017.8280362
Chin-Wei Hsu, Chien-Hung Tsai, Kai-Yu Hu
A digital control dc-dc buck converter with dual voltage feedback loop is presented to achieve good transient performance. Unlike conventional voltage mode buck converter which uses linear controller, such as PID control, the transient response is limited by the control bandwidth and switching frequency. The proposed dual loop system adds an extra control loop with charge control technique to improve the transient response. Also, the transient output voltage of the buck converter can be suppressed under 3.5% of the output voltage. The digital controller is implemented by FPGA and power stage is implemented by PCB with discrete component. Experimental results demonstrate the superior transient output voltage over that of a conventional linear controller.
{"title":"Low transient voltage dual loop buck converter using digital charge control technique","authors":"Chin-Wei Hsu, Chien-Hung Tsai, Kai-Yu Hu","doi":"10.1109/PRIMEASIA.2017.8280362","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280362","url":null,"abstract":"A digital control dc-dc buck converter with dual voltage feedback loop is presented to achieve good transient performance. Unlike conventional voltage mode buck converter which uses linear controller, such as PID control, the transient response is limited by the control bandwidth and switching frequency. The proposed dual loop system adds an extra control loop with charge control technique to improve the transient response. Also, the transient output voltage of the buck converter can be suppressed under 3.5% of the output voltage. The digital controller is implemented by FPGA and power stage is implemented by PCB with discrete component. Experimental results demonstrate the superior transient output voltage over that of a conventional linear controller.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134049853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/PRIMEASIA.2017.8280376
Mohammed Mazharuddin Harsoori, T. Zulkifli, Umber Abbas, Sami Sattar
This paper presents the design of 60 GHz low noise amplifier (LNA) aimed at realizing IEEE 802.11ad standard using 0.13-μm RF CMOS technology. Single stage cascode with source degeneration topology employing a gain boosting technique is adopted for better isolation and gain performance in millimeter-wave (mmW) frequency band. The simulation of the LNA yields the input reflection coefficient (S11) of −20.75 dB, forward transmission gain (S21) of 7.75 dB, and reverse isolation (£12) of 8.64 dB. The LNA design achieves a noise figure (NF) of 8.9 dB with minimum noise figure (NFmin) of 7.8 dB at 60 GHz. Thus, the design generates power dissipation of 15.17 mW for 1.2 V supply voltage.
{"title":"A gain boosting single stage cascode LNA for millimeter-wave applications","authors":"Mohammed Mazharuddin Harsoori, T. Zulkifli, Umber Abbas, Sami Sattar","doi":"10.1109/PRIMEASIA.2017.8280376","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280376","url":null,"abstract":"This paper presents the design of 60 GHz low noise amplifier (LNA) aimed at realizing IEEE 802.11ad standard using 0.13-μm RF CMOS technology. Single stage cascode with source degeneration topology employing a gain boosting technique is adopted for better isolation and gain performance in millimeter-wave (mmW) frequency band. The simulation of the LNA yields the input reflection coefficient (S11) of −20.75 dB, forward transmission gain (S21) of 7.75 dB, and reverse isolation (£12) of 8.64 dB. The LNA design achieves a noise figure (NF) of 8.9 dB with minimum noise figure (NFmin) of 7.8 dB at 60 GHz. Thus, the design generates power dissipation of 15.17 mW for 1.2 V supply voltage.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124113776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/PRIMEASIA.2017.8280351
M. M. Latha, R. Rachh, P. Mohan
In this paper, a RNS (Residue Number System) to Binary converter for the three-moduli set {2n−1−1, 2n+k, 2n−1} using two-stage Mixed Radix Conversion (MRC) is presented. Two separate cases (a) 0 ≤ k ≤ n-2, and (b) k = n−1, k = n lead to two different reverse converters. The proposed reverse converters are evaluated and compared with state of the art reverse converters proposed for this moduli set regarding hardware requirement and conversion time.
本文利用两级混合基数转换(MRC)，给出了三模集{2n−1−1,2n +k, 2n−1}的RNS(残数系统)到二进制的转换。(a) 0≤k≤n-2， (b) k = n−1,k = n两种不同的情况导致两个不同的反向变换器。在硬件要求和转换时间方面，对所提出的逆变器进行了评估，并与该模组所提出的最先进的逆变器进行了比较。
{"title":"An efficient residue-to-binary converter for the moduli set {2n−1−1, 2n+k, 2n−1}","authors":"M. M. Latha, R. Rachh, P. Mohan","doi":"10.1109/PRIMEASIA.2017.8280351","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280351","url":null,"abstract":"In this paper, a RNS (Residue Number System) to Binary converter for the three-moduli set {2<sup>n−1</sup>−1, 2<sup>n+k</sup>, 2<sup>n</sup>−1} using two-stage Mixed Radix Conversion (MRC) is presented. Two separate cases (a) 0 ≤ k ≤ n-2, and (b) k = n−1, k = n lead to two different reverse converters. The proposed reverse converters are evaluated and compared with state of the art reverse converters proposed for this moduli set regarding hardware requirement and conversion time.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"56 77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131536306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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