Networking industry trends in ESD protection for high speed IOs

Abstract

Data rates in networking applications have increased as demand for more data increases. To achieve the high performance, the data rates in high speed IOs have continued to increase. These high data rates require the IO capacitances have to be very low. ESD protection structures have traditionally been large to handle the large transient currents. Recently, the high speed IO has limited the capacitance associated with ESD structures, making ESD protection design for high speed IOs extremely challenging. This paper will discuss the networking industry's trends in high speed IOs, the capacitance requirements and resulting challenges for ESD protection designs. To achieve the proper ESD protection, on chip ESD protection schemes will need to change and/or ESD protection specifications may need to lower targeted protection levels. This is a hotly argued topic in the high speed networking industry, which may change the next-generation ESD protection design dramatically. We will discuss the possible ESD design outcomes due to the high speed IOs scaling trends.