Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812028
Yusen Xu, Wei Hu, F. Huang, Jiwei Huang
A new low-power voltage reference circuit was proposed using the SMIC 0.18um standard CMOS process technology. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at 0K, which was about 620mV for this process. Cadence Spectre simulation results show that the temperature coefficient of the output voltage was 12.9ppm/° in a range from -20 to 80°. The line sensitivity was 328ppm/V in a supply voltage range of 1.2-3V. Meanwhile - 68 dB @ 100Hz of the power supply rejection ratio (PSRR) is reached and it merely consumes 0.21 μ W of power. The proposed circuit is full composed of CMOS devices without any use of resistors, which enjoys the merits of low power consumption and small chip area.
采用中芯国际0.18um标准CMOS工艺技术，提出了一种新的低功耗电压基准电路。所得电压等于在0K时MOSFET的外推阈值电压，该过程约为620mV。Cadence Spectre仿真结果表明，在-20 ~ 80°范围内，输出电压的温度系数为12.9ppm/°。在电源电压1.2-3V范围内，线路灵敏度为328ppm/V。同时，电源抑制比(PSRR)达到- 68 dB @ 100Hz，功耗仅为0.21 μ W。该电路完全由CMOS器件组成，不使用任何电阻，具有功耗低、芯片面积小的优点。
{"title":"Design of a novel all-CMOS low power voltage reference circuit","authors":"Yusen Xu, Wei Hu, F. Huang, Jiwei Huang","doi":"10.1109/ASICON.2013.6812028","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812028","url":null,"abstract":"A new low-power voltage reference circuit was proposed using the SMIC 0.18um standard CMOS process technology. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at 0K, which was about 620mV for this process. Cadence Spectre simulation results show that the temperature coefficient of the output voltage was 12.9ppm/° in a range from -20 to 80°. The line sensitivity was 328ppm/V in a supply voltage range of 1.2-3V. Meanwhile - 68 dB @ 100Hz of the power supply rejection ratio (PSRR) is reached and it merely consumes 0.21 μ W of power. The proposed circuit is full composed of CMOS devices without any use of resistors, which enjoys the merits of low power consumption and small chip area.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123046156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811861
B. Wang, Guoyi Yu, Xiaofei Chen, Li Zhang, Xavier Zou
A accuracy physical model and Greenhouse algorithm is presented in this paper in 3D package. A relative simple and fast method of calculation the coupling inductors coefficient is presented in this paper. The parameters of the inductors coupling is high efficiency are discussed. The appropriate position is calculated where the interference of inductor channel is minimum in the 3D package.
{"title":"Analysis inductively coupling wireless connection in 3D package","authors":"B. Wang, Guoyi Yu, Xiaofei Chen, Li Zhang, Xavier Zou","doi":"10.1109/ASICON.2013.6811861","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811861","url":null,"abstract":"A accuracy physical model and Greenhouse algorithm is presented in this paper in 3D package. A relative simple and fast method of calculation the coupling inductors coefficient is presented in this paper. The parameters of the inductors coupling is high efficiency are discussed. The appropriate position is calculated where the interference of inductor channel is minimum in the 3D package.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123138523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811860
Y. Deval, F. Rivet, Yoan Veyrac, Nicolas Regimbal, P. Garrec, Richard Montigny, D. Belot, T. Taris
This paper presents the current status and trends in research on Full Software Radio (FSR). Concerning the receiver path after defining Software Defined Radio (SDR) versus FSR a new version of the Sampled Analog Signal Processor (SASP) is presented and experimental results are discussed. The new version doubles the signal bandwidth while the power consumption is reduced to less than 100 mW. For the transmitter path, a new FSR architecture is presented based on Riemann's algorithm and a charge pump. A GaN demonstrator of the Riemann's Pump is presented, which generates any signal including concurrent emissions in the 0-to-1 GHz band.
{"title":"Full Software Radio transceivers","authors":"Y. Deval, F. Rivet, Yoan Veyrac, Nicolas Regimbal, P. Garrec, Richard Montigny, D. Belot, T. Taris","doi":"10.1109/ASICON.2013.6811860","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811860","url":null,"abstract":"This paper presents the current status and trends in research on Full Software Radio (FSR). Concerning the receiver path after defining Software Defined Radio (SDR) versus FSR a new version of the Sampled Analog Signal Processor (SASP) is presented and experimental results are discussed. The new version doubles the signal bandwidth while the power consumption is reduced to less than 100 mW. For the transmitter path, a new FSR architecture is presented based on Riemann's algorithm and a charge pump. A GaN demonstrator of the Riemann's Pump is presented, which generates any signal including concurrent emissions in the 0-to-1 GHz band.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115339923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811984
Hengzhou Yuan, Zhuo Ma, Yang Guo
The demand for high-speed low-power multi-modulus frequency divider is increasing in Phase-Locked Loop (PLL) design. In this paper, by combining the merits of traditional Johnson counter and Pulse-swallow frequency divider, we proposed a novel two-stage divider which can improve the operating frequency and decrease the power dissipation enormously. An adaptive component is built to set the divider in best power-saving mode. Based on the 40nm CMOS process, the frequency of this two-stage divider can reach 4GHz. The minimum power dissipation in divide-by-49 mode is 63μW@1GHz, or 156μW@4GHz. Compared with typical Johnson counter frequency divider, the frequency of the two-stage divider is improved about 1.6 times, while the power optimization ratio is 51.19%.
{"title":"An adaptive multi-modulus frequency divider","authors":"Hengzhou Yuan, Zhuo Ma, Yang Guo","doi":"10.1109/ASICON.2013.6811984","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811984","url":null,"abstract":"The demand for high-speed low-power multi-modulus frequency divider is increasing in Phase-Locked Loop (PLL) design. In this paper, by combining the merits of traditional Johnson counter and Pulse-swallow frequency divider, we proposed a novel two-stage divider which can improve the operating frequency and decrease the power dissipation enormously. An adaptive component is built to set the divider in best power-saving mode. Based on the 40nm CMOS process, the frequency of this two-stage divider can reach 4GHz. The minimum power dissipation in divide-by-49 mode is 63μW@1GHz, or 156μW@4GHz. Compared with typical Johnson counter frequency divider, the frequency of the two-stage divider is improved about 1.6 times, while the power optimization ratio is 51.19%.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116153917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812007
Qi Yang, Xiaoting Hu, Zhongping Qin
A novel secure architecture of secure systolic Montgomery modular multiplier resilient to Fault-Injection attacks is proposed. The proposed architecture has been verified by modeling, implementing and testing it using VHDL. The error mask probability is under 0.0015% when we set the check integer properly. The performances of proposed architecture are comparable to those of other schemes in literature, where the hardware overheads vary from 5.68% to 46.44% in different types of implementations, and the time overheads are close to 0.
{"title":"Secure systolic architecture for montgomery modular multiplication algorithm","authors":"Qi Yang, Xiaoting Hu, Zhongping Qin","doi":"10.1109/ASICON.2013.6812007","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812007","url":null,"abstract":"A novel secure architecture of secure systolic Montgomery modular multiplier resilient to Fault-Injection attacks is proposed. The proposed architecture has been verified by modeling, implementing and testing it using VHDL. The error mask probability is under 0.0015% when we set the check integer properly. The performances of proposed architecture are comparable to those of other schemes in literature, where the hardware overheads vary from 5.68% to 46.44% in different types of implementations, and the time overheads are close to 0.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117291155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811949
Xiaofei Chen, Yading Shen, X. Zou, Shuang-Xi Lin, Wanghui Zou
An improved radio-frequency (RF) lateral double-diffused metal-oxide-semiconductor (LDMOS) device based on Si-substrate process is proposed. The structure is characterized by a p+-buried-layer (PBL) buried under the drain in the p-substrate region. A vertical n+n-p-p+ diode formed at the drain side helps deplete the n-drift region and lengthen the lateral drift distance, thus effectively increasing the device breakdown voltage (BVDS) with negligible disturbances to the on-resistance (Ron) and RF performance as the PBL is far away from the carrier channel. Both theoretical analysis and simulations of PBL effects are demonstrated. Compared with the conventional device, the proposed RF-LDMOS device increase by 19.8% and 12.2% in BVDS and BVDS*ft, respectively.
{"title":"A new high performance RF LDMOS with vertical n+n-p-p+ drain structure","authors":"Xiaofei Chen, Yading Shen, X. Zou, Shuang-Xi Lin, Wanghui Zou","doi":"10.1109/ASICON.2013.6811949","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811949","url":null,"abstract":"An improved radio-frequency (RF) lateral double-diffused metal-oxide-semiconductor (LDMOS) device based on Si-substrate process is proposed. The structure is characterized by a p<sup>+</sup>-buried-layer (PBL) buried under the drain in the p-substrate region. A vertical n<sup>+</sup>n<sup>-</sup>p<sup>-</sup>p<sup>+</sup> diode formed at the drain side helps deplete the n-drift region and lengthen the lateral drift distance, thus effectively increasing the device breakdown voltage (BV<sub>DS</sub>) with negligible disturbances to the on-resistance (R<sub>on</sub>) and RF performance as the PBL is far away from the carrier channel. Both theoretical analysis and simulations of PBL effects are demonstrated. Compared with the conventional device, the proposed RF-LDMOS device increase by 19.8% and 12.2% in BV<sub>DS</sub> and BV<sub>DS</sub>*f<sub>t</sub>, respectively.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129520581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Two gate-voltage-bias techniques for gate-coupled MOS (gcMOS) electrostatic discharge (ESD) protection circuits are proposed in this paper. The proposed techniques bias the gate voltage of discharging transistor to approximately half of its drain voltage during an ESD event through either subtraction circuit elements or division circuit elements in order to achieve highest second breakdown current (It2) levels. Besides, leakage current levels of protection circuits with proposed gate-voltage-bias techniques are verified to be smaller than that of the traditional design.
{"title":"Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits","authors":"Guangyi Lu, Yuan Wang, Jian Cao, S. Jia, Ganggang Zhang, Xing Zhang","doi":"10.1109/ASICON.2013.6811960","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811960","url":null,"abstract":"Two gate-voltage-bias techniques for gate-coupled MOS (gcMOS) electrostatic discharge (ESD) protection circuits are proposed in this paper. The proposed techniques bias the gate voltage of discharging transistor to approximately half of its drain voltage during an ESD event through either subtraction circuit elements or division circuit elements in order to achieve highest second breakdown current (It2) levels. Besides, leakage current levels of protection circuits with proposed gate-voltage-bias techniques are verified to be smaller than that of the traditional design.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130619502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812012
Yong-xu Zhu, Bin Wu, Yumei Zhou, Kaifeng Xia, Lu Sun
Due to the growing demand of transmission capacity of the wireless communication system, multiple-input multiple-output orthogonal frequency division multiplexing requires more and more antennas and a large number of sub-carriers. Thus, the QR decomposition becomes one of the computational bottlenecks in the QR-based MIMO detection because of calculating latency of many sub-carriers and compatible structure for different antennas. The proposed configurable distributed systolic array structure uses coordinate rotation digital computer computation in the boundary and internal cells of systolic array, and distributes the QR decomposition of different sub-carriers into the different stages of the pipelining operation of CORDIC in systolic array. The structure has good scalability for antennas of different dimension, and the latency outperforms other works in the literature.
{"title":"A configurable distributed systolic array for QR decomposition in MIMO-OFDM systems","authors":"Yong-xu Zhu, Bin Wu, Yumei Zhou, Kaifeng Xia, Lu Sun","doi":"10.1109/ASICON.2013.6812012","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812012","url":null,"abstract":"Due to the growing demand of transmission capacity of the wireless communication system, multiple-input multiple-output orthogonal frequency division multiplexing requires more and more antennas and a large number of sub-carriers. Thus, the QR decomposition becomes one of the computational bottlenecks in the QR-based MIMO detection because of calculating latency of many sub-carriers and compatible structure for different antennas. The proposed configurable distributed systolic array structure uses coordinate rotation digital computer computation in the boundary and internal cells of systolic array, and distributes the QR decomposition of different sub-carriers into the different stages of the pipelining operation of CORDIC in systolic array. The structure has good scalability for antennas of different dimension, and the latency outperforms other works in the literature.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120884933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812018
Shili Wu, Xiaowei He, Yuwei Liu, Guoan Chen
In this work, polarity dependent of gate oxide breakdown is investigated for both NMOS and PMOS in a large range of oxide thicknesses, 27Å, 170Å and 850Å. All the devices are measured using constant voltage stress (CVS) method. From the measurements, It is found that for thick gate oxide, lifetime (TBD) under negative gate bias is always shorter regardless of the types of the MOSFETs. However, when the oxide thickness scaled down, the accumulation case gets shorter lifetime than the inversion case for both NMOS and PMOS. In addition, the gate current changes over the stress time for different oxide thicknesses are also exhibited which imply different breakdown processes.
{"title":"Polarity dependent of gate oxide breakdown from measurements","authors":"Shili Wu, Xiaowei He, Yuwei Liu, Guoan Chen","doi":"10.1109/ASICON.2013.6812018","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812018","url":null,"abstract":"In this work, polarity dependent of gate oxide breakdown is investigated for both NMOS and PMOS in a large range of oxide thicknesses, 27Å, 170Å and 850Å. All the devices are measured using constant voltage stress (CVS) method. From the measurements, It is found that for thick gate oxide, lifetime (TBD) under negative gate bias is always shorter regardless of the types of the MOSFETs. However, when the oxide thickness scaled down, the accumulation case gets shorter lifetime than the inversion case for both NMOS and PMOS. In addition, the gate current changes over the stress time for different oxide thicknesses are also exhibited which imply different breakdown processes.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121174340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811841
M. Hashimoto
This paper discusses soft error immunity of subthreshold SRAM presenting neutron- and alpha-induced soft error rates (SER) in 65-nm 10T SRAM over a wide range of supply voltages from 1.0 to 0.3 V. The results show that the neutron-induced SER at 0.3 V is 7.8 times as high as that at 1.0 V. The measured multiple cell upsets (MCUs) included 8-bit MCU. With 0.4V operation of the SRAM under test, protons are not dominant secondary particles causing SEU, but this paper points out that protons must be considered for future near-threshold computing. The alpha-induced SER at 0.3V is 6x higher than that at 1.0V. These results can contribute to reliability estimation and enhancement in subthreshold circuit design.
{"title":"Soft error immunity of subthreshold SRAM","authors":"M. Hashimoto","doi":"10.1109/ASICON.2013.6811841","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811841","url":null,"abstract":"This paper discusses soft error immunity of subthreshold SRAM presenting neutron- and alpha-induced soft error rates (SER) in 65-nm 10T SRAM over a wide range of supply voltages from 1.0 to 0.3 V. The results show that the neutron-induced SER at 0.3 V is 7.8 times as high as that at 1.0 V. The measured multiple cell upsets (MCUs) included 8-bit MCU. With 0.4V operation of the SRAM under test, protons are not dominant secondary particles causing SEU, but this paper points out that protons must be considered for future near-threshold computing. The alpha-induced SER at 0.3V is 6x higher than that at 1.0V. These results can contribute to reliability estimation and enhancement in subthreshold circuit design.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121323780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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