{"title":"A charge pump current missmatch calibration technique for ΔΣ fractional-N PLLs in 0.18-μm CMOS","authors":"W. Chiu, Tai-Shun Chang, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2009.5357182","DOIUrl":null,"url":null,"abstract":"This work presents a charge pump (CP) calibration technique for a Delta-Sigma fractional-N phase-locked loop (ΣΔ-FNPLL). The proposed calibration method introduces an auxiliary path to the CP circuit and utilizes some interval within each reference cycle to detect the mismatch and then correct the up/down current difference. The proposed CP calibration is employed in the design of a 2.4-GHz ΣΔ-FNPLL. The experimental result has demonstrated that the in-band phase noise and fractional spurs are significantly reduced when the proposed CP calibration is activated. Fabricated in a TSMC 0.18-μm CMOS process, the whole ΣΔ-FNPLL consumes 23 mW from a 1.8-V supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357182","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This work presents a charge pump (CP) calibration technique for a Delta-Sigma fractional-N phase-locked loop (ΣΔ-FNPLL). The proposed calibration method introduces an auxiliary path to the CP circuit and utilizes some interval within each reference cycle to detect the mismatch and then correct the up/down current difference. The proposed CP calibration is employed in the design of a 2.4-GHz ΣΔ-FNPLL. The experimental result has demonstrated that the in-band phase noise and fractional spurs are significantly reduced when the proposed CP calibration is activated. Fabricated in a TSMC 0.18-μm CMOS process, the whole ΣΔ-FNPLL consumes 23 mW from a 1.8-V supply.
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