Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357239
Seokyong Hong, Tae-Shin Kang, Myung-woon Hwang, Sungho Beck, Jeong-Cheol Lee, Moonkyung Ahn, Hyunha Jo, Seungbum Lim, T. Kim, Sangjin Lee, S. Yoo, Jong-Ryul Lee, Sangwoo Han
This paper presents a 1.8V 300mW System-In-Package (SiP) solution in mobile S-DMB application. This achieves a 1.8 dB noise figure at 2.6GHz, while the measured sensitivity is −101 dBm at diversity mode. The SiP is integrated RF tuner, demodulator, SDRAM and other passive components. An internal AGC is integrated for over 100dB dynamic range. The SiP is 196 pins LFBGA and the size is 10 mm × 10 mm × 1.3 mm. The SiP consumes 300mW.
{"title":"A 1.8dB NF 300mW SiP for 2.6GHz diversity S-DMB application","authors":"Seokyong Hong, Tae-Shin Kang, Myung-woon Hwang, Sungho Beck, Jeong-Cheol Lee, Moonkyung Ahn, Hyunha Jo, Seungbum Lim, T. Kim, Sangjin Lee, S. Yoo, Jong-Ryul Lee, Sangwoo Han","doi":"10.1109/ASSCC.2009.5357239","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357239","url":null,"abstract":"This paper presents a 1.8V 300mW System-In-Package (SiP) solution in mobile S-DMB application. This achieves a 1.8 dB noise figure at 2.6GHz, while the measured sensitivity is −101 dBm at diversity mode. The SiP is integrated RF tuner, demodulator, SDRAM and other passive components. An internal AGC is integrated for over 100dB dynamic range. The SiP is 196 pins LFBGA and the size is 10 mm × 10 mm × 1.3 mm. The SiP consumes 300mW.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115288936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357155
Daichi Kaku, T. Namekawa, K. Matsufuji, O. Wada, H. Ito, Y. Sugisawa, Sakiko Shimizu, Takeshi Yamamoto, Kenji Honda, M. Hamada, K. Numata
A Pure CMOS One-time Programmable memory (PCOP) macro using a PMOS antifuse is designed for field programming. In this work, a Temperature-controlled programming Voltage Generator (TVG) realizes field programming by improving programming characteristics over a wide temperature range, from −40° C to 125° C, and supply voltage variations of ±10%. In addition, the memory cell dimensions are optimized and reduced by 40%, which also results in better reading characteristics. PCOP has a 16-Kbit capacity, uses 1.1-V and 3.3-V power sources, occupies 0.224 mm and is implemented in a 40-nm pure CMOS logic technology with thin and thick oxide film transistors.
{"title":"A field programmable 40-nm pure CMOS embedded memory macro using a PMOS antifuse","authors":"Daichi Kaku, T. Namekawa, K. Matsufuji, O. Wada, H. Ito, Y. Sugisawa, Sakiko Shimizu, Takeshi Yamamoto, Kenji Honda, M. Hamada, K. Numata","doi":"10.1109/ASSCC.2009.5357155","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357155","url":null,"abstract":"A Pure CMOS One-time Programmable memory (PCOP) macro using a PMOS antifuse is designed for field programming. In this work, a Temperature-controlled programming Voltage Generator (TVG) realizes field programming by improving programming characteristics over a wide temperature range, from −40° C to 125° C, and supply voltage variations of ±10%. In addition, the memory cell dimensions are optimized and reduced by 40%, which also results in better reading characteristics. PCOP has a 16-Kbit capacity, uses 1.1-V and 3.3-V power sources, occupies 0.224 mm and is implemented in a 40-nm pure CMOS logic technology with thin and thick oxide film transistors.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115609485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a successive approximation analog-to-digital converter (SAR ADC) achieving high power efficiency by adopting sub-range concept. Overlapping range greatly relieves the accuracy requirement on the first 6 bit resolving in coarse conversion. The error made in the coarse conversion is recovered during the rest 7 bit resolving in fine conversion. Hence, it significantly reduces the capacitor array output settling time of most-significant-bit (MSB) capacitor switching, which is the speed bottleneck for traditional SAR ADC. A 3mW 12b 10MS/s sub-range SAR ADC is realized in 0.13-μm CMOS process. The prototype circuit reaches SNDR 59.7dB at Nyquist input frequency. It occupies an active chip area of 0.096 mm2.
{"title":"A 3mW 12b 10MS/s sub-range SAR ADC","authors":"Hung-Wei Chen, Yu-Hsun Liu, Yu-Hsiang Lin, Hsin-Shu Chen","doi":"10.1109/ASSCC.2009.5357201","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357201","url":null,"abstract":"This paper presents a successive approximation analog-to-digital converter (SAR ADC) achieving high power efficiency by adopting sub-range concept. Overlapping range greatly relieves the accuracy requirement on the first 6 bit resolving in coarse conversion. The error made in the coarse conversion is recovered during the rest 7 bit resolving in fine conversion. Hence, it significantly reduces the capacitor array output settling time of most-significant-bit (MSB) capacitor switching, which is the speed bottleneck for traditional SAR ADC. A 3mW 12b 10MS/s sub-range SAR ADC is realized in 0.13-μm CMOS process. The prototype circuit reaches SNDR 59.7dB at Nyquist input frequency. It occupies an active chip area of 0.096 mm2.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"357 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122827431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357217
Chang-Lin Hsieh, Hong-Lin Chu, Shen-Iuan Liu
A 10Gb/s inductorless quarter-rate clock and data recovery (CDR) circuit is presented. In this CDR circuit, a triggering generator is proposed to realize the quarter-rate operation. Owing to the quarter-rate operation and the absence of inductors, this CDR circuit achieves low power consumption and small area simultaneously. This 10Gb/s quarter-rate CDR circuit has been fabricated in a 0.13um CMOS process. It recovers the data and clock within 5 bits. The measured peak-to-peak jitter of the recovered data and clock is 32.22ps and 30.7ps, respectively. The chip area including a PLL and a dummy GVCO is 0.2mm2. This CDR circuit consumes 122.5mW excluding output buffers from a supply voltage of 1.5V.
{"title":"A 10Gb/s inductorless quarter-rate clock and data recovery circuit in 0.13um CMOS","authors":"Chang-Lin Hsieh, Hong-Lin Chu, Shen-Iuan Liu","doi":"10.1109/ASSCC.2009.5357217","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357217","url":null,"abstract":"A 10Gb/s inductorless quarter-rate clock and data recovery (CDR) circuit is presented. In this CDR circuit, a triggering generator is proposed to realize the quarter-rate operation. Owing to the quarter-rate operation and the absence of inductors, this CDR circuit achieves low power consumption and small area simultaneously. This 10Gb/s quarter-rate CDR circuit has been fabricated in a 0.13um CMOS process. It recovers the data and clock within 5 bits. The measured peak-to-peak jitter of the recovered data and clock is 32.22ps and 30.7ps, respectively. The chip area including a PLL and a dummy GVCO is 0.2mm2. This CDR circuit consumes 122.5mW excluding output buffers from a supply voltage of 1.5V.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129354608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357260
W. Deng, R. Mahmoudi, A. V. van Roermund, F. Fortes, E. van der Heijden
This paper presents a fully integrated receiver front-end for time-division multiplexing phased-array system. The 30GHz front-end includes a low-noise amplifier (LNA), a 4:1 multiplexer, a mixer, and a clock sequencer. The circuit has been implemented in a 0.25μm, 130GHz-fT SiGe process. The front-end shows a input reflection coefficient (S11) of −20dB, a minimum measured LNA-Multiplexer noise figure (NF) of 4.1dB, and a maximum conversion gain (CG) of 18.9dB at 30GHz. Measurements show a 1dB input compression point of −32.3dBm, a third order intercept point (IIP3) of −22dBm, and a channel isolation of 23dB at 30GHz. This system reduces receiver power consumption by reducing ADC numbers.
{"title":"A 30GHz integrated time-division multiplexing front-end for phased-array applications in SiGe","authors":"W. Deng, R. Mahmoudi, A. V. van Roermund, F. Fortes, E. van der Heijden","doi":"10.1109/ASSCC.2009.5357260","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357260","url":null,"abstract":"This paper presents a fully integrated receiver front-end for time-division multiplexing phased-array system. The 30GHz front-end includes a low-noise amplifier (LNA), a 4:1 multiplexer, a mixer, and a clock sequencer. The circuit has been implemented in a 0.25μm, 130GHz-fT SiGe process. The front-end shows a input reflection coefficient (S11) of −20dB, a minimum measured LNA-Multiplexer noise figure (NF) of 4.1dB, and a maximum conversion gain (CG) of 18.9dB at 30GHz. Measurements show a 1dB input compression point of −32.3dBm, a third order intercept point (IIP3) of −22dBm, and a channel isolation of 23dB at 30GHz. This system reduces receiver power consumption by reducing ADC numbers.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124253539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357182
W. Chiu, Tai-Shun Chang, Tsung-Hsien Lin
This work presents a charge pump (CP) calibration technique for a Delta-Sigma fractional-N phase-locked loop (ΣΔ-FNPLL). The proposed calibration method introduces an auxiliary path to the CP circuit and utilizes some interval within each reference cycle to detect the mismatch and then correct the up/down current difference. The proposed CP calibration is employed in the design of a 2.4-GHz ΣΔ-FNPLL. The experimental result has demonstrated that the in-band phase noise and fractional spurs are significantly reduced when the proposed CP calibration is activated. Fabricated in a TSMC 0.18-μm CMOS process, the whole ΣΔ-FNPLL consumes 23 mW from a 1.8-V supply.
{"title":"A charge pump current missmatch calibration technique for ΔΣ fractional-N PLLs in 0.18-μm CMOS","authors":"W. Chiu, Tai-Shun Chang, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2009.5357182","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357182","url":null,"abstract":"This work presents a charge pump (CP) calibration technique for a Delta-Sigma fractional-N phase-locked loop (ΣΔ-FNPLL). The proposed calibration method introduces an auxiliary path to the CP circuit and utilizes some interval within each reference cycle to detect the mismatch and then correct the up/down current difference. The proposed CP calibration is employed in the design of a 2.4-GHz ΣΔ-FNPLL. The experimental result has demonstrated that the in-band phase noise and fractional spurs are significantly reduced when the proposed CP calibration is activated. Fabricated in a TSMC 0.18-μm CMOS process, the whole ΣΔ-FNPLL consumes 23 mW from a 1.8-V supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114204310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357234
S. Morris, Alastair Lefley
This paper presents the design of a 90nm 13.56MHz NFC Transceiver. The concept of Near Field Communication is introduced while discussing how a combination of both Initiator and Target functions are required. The Initiator circuitry used to generate the required magnetic field and demodulate the received back-scatter is explained and the passive and active Target circuitry used to receive a magnetic field whilst demodulating and load-modulating is presented. Finally there is a short description of the Evaluation Module (EVM) containing the 90nm NFC, an antenna and interface to a host processor or PC.
{"title":"A 90nm CMOS 13.56MHz NFC transceiver","authors":"S. Morris, Alastair Lefley","doi":"10.1109/ASSCC.2009.5357234","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357234","url":null,"abstract":"This paper presents the design of a 90nm 13.56MHz NFC Transceiver. The concept of Near Field Communication is introduced while discussing how a combination of both Initiator and Target functions are required. The Initiator circuitry used to generate the required magnetic field and demodulate the received back-scatter is explained and the passive and active Target circuitry used to receive a magnetic field whilst demodulating and load-modulating is presented. Finally there is a short description of the Evaluation Module (EVM) containing the 90nm NFC, an antenna and interface to a host processor or PC.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131789507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357254
Bo Yu, Xiangyu Li, Naiwen Zhang, Yihe Sun
THUAES06 that implements the standard AES algorithm is characterized by low cost, low power and high differential power analysis (DPA) resisting ability enhancement. The DPA resisting ability enhancement is achieved by using fine grained shuffling as the DPA countermeasure of the main part and implementing vulnerable function unit with dual rail asynchronous circuits. THUAES06 is implemented in SMIC 0.18 μm technology. Its average energy of encrypting or decrypting one 128 bits plaintext or cipher text is 19nJ if initial key need not be changed. Its core area is 0.43mm2. The power traces needed to disclose the secrete keys are more than 33,000.
{"title":"A low cost, low power AES ASIC with high DPA resisting ability","authors":"Bo Yu, Xiangyu Li, Naiwen Zhang, Yihe Sun","doi":"10.1109/ASSCC.2009.5357254","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357254","url":null,"abstract":"THUAES06 that implements the standard AES algorithm is characterized by low cost, low power and high differential power analysis (DPA) resisting ability enhancement. The DPA resisting ability enhancement is achieved by using fine grained shuffling as the DPA countermeasure of the main part and implementing vulnerable function unit with dual rail asynchronous circuits. THUAES06 is implemented in SMIC 0.18 μm technology. Its average energy of encrypting or decrypting one 128 bits plaintext or cipher text is 19nJ if initial key need not be changed. Its core area is 0.43mm2. The power traces needed to disclose the secrete keys are more than 33,000.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123655426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357150
Tsung-Huang Chen, Jason C. Chen, Teng-Yuan Cheng, Shao-Yi Chien
A 329mW 600M-Pixels/s dual-stream coarsegrained reconfigurable image stream processor is implemented in TSMC 0.13μm CMOS technology with a core size of 4.84mm2. The reconfigurable pipelined processing element array architecture makes a good balance between computing performance and flexibility with only 10Kb on-chip memory. Moreover, a new dual-stream architecture is proposed to improve the flexibility and hardware efficiency by processing two independent image streams with two-layer context switching, and an isolation technique is also proposed to improve the power consumption. Implementation results show that it achieves 1.52 times power efficiency than previous works and can meet the requirements of high-definition video camcorders and digital still cameras.
{"title":"CRISP-DS: Dual-stream coarse-grained reconfigurable image stream processor for HD digital camcorders and digital still cameras","authors":"Tsung-Huang Chen, Jason C. Chen, Teng-Yuan Cheng, Shao-Yi Chien","doi":"10.1109/ASSCC.2009.5357150","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357150","url":null,"abstract":"A 329mW 600M-Pixels/s dual-stream coarsegrained reconfigurable image stream processor is implemented in TSMC 0.13μm CMOS technology with a core size of 4.84mm2. The reconfigurable pipelined processing element array architecture makes a good balance between computing performance and flexibility with only 10Kb on-chip memory. Moreover, a new dual-stream architecture is proposed to improve the flexibility and hardware efficiency by processing two independent image streams with two-layer context switching, and an isolation technique is also proposed to improve the power consumption. Implementation results show that it achieves 1.52 times power efficiency than previous works and can meet the requirements of high-definition video camcorders and digital still cameras.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125980509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357179
Seongwoong Lim, Wasanthamala Badalawa, M. Fujishima
An inductor-less 110GHz ring-type frequency divider (RILFD) has been proposed. Body-injection and biasing technique have been adopted to achieve high speed and divide-by-three operation and fine tuning of operation frequency. The RILFD was fabricated by a 1P12M 65nm bulk CMOS process. The core size is 10.8×8.5μm2. The locking range is 9.1%, from 100.8 to 110.4GHz, under varying of body-bias voltage from −0.2V to 0.4V. The RILFD consumes 4.5mW at the supply voltage of 1V excluding an output buffer. The output phase noise is −117.6dBc/Hz at 1MHz offset. This work has been achieved the smallest core size among frequency dividers reported to date operating over 100GHz.
{"title":"A 110GHz inductor-less CMOS frequency divider","authors":"Seongwoong Lim, Wasanthamala Badalawa, M. Fujishima","doi":"10.1109/ASSCC.2009.5357179","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357179","url":null,"abstract":"An inductor-less 110GHz ring-type frequency divider (RILFD) has been proposed. Body-injection and biasing technique have been adopted to achieve high speed and divide-by-three operation and fine tuning of operation frequency. The RILFD was fabricated by a 1P12M 65nm bulk CMOS process. The core size is 10.8×8.5μm2. The locking range is 9.1%, from 100.8 to 110.4GHz, under varying of body-bias voltage from −0.2V to 0.4V. The RILFD consumes 4.5mW at the supply voltage of 1V excluding an output buffer. The output phase noise is −117.6dBc/Hz at 1MHz offset. This work has been achieved the smallest core size among frequency dividers reported to date operating over 100GHz.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128523863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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