A dynamic logic circuit embedded flip-flop for ASIC design

Abstract

We report a flip-flop with a dynamic logic circuit for data path designed with standard cell. The flip-flop provides fast logic operation by the dynamic logic circuit and reduces total power dissipation of a data path by suppressing glitches. An absolute difference unit for motion estimation is used in a benchmark test. By using the flip-flop, the unit is 20% to 40% faster and has 20% to 50% less power dissipation than when conventional D-FFs are used.