Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896939
Young-ho Seo, Jong-Hyeon Kim, Dong-Wook Kim
This paper presents a hardware implementation of SEED, which is a Korean standard 128-bit symmetric block cipher: the target of the design was FPGA, but SEED was designed technology-independently for other applications such as ASIC or core-based designs. Hence in the case of changing the target of design, it is not necessary to modify design or to need minor modification in order to reuse the design. The design consists of round key generation part, F-function part, control part and round process part. Since SEED algorithm requires a lot of hardware resources, each unit was designed only once, except S-Box, and operated sequentially. Therefore the number of gates was minimized and SEED algorithm was fitted in FPGA without additional components. Also it was confirmed that the rate of resource usage is about 80% in ALTERA 10 KE. The design was synthesized in SYNOPSYS synthesis tool using ALTERA 10 K library and was simulated in MAX+PLUSII FPGA tool. The SEED design operates in a clock frequency of 5 MHz and uses 145 clocks. So encryption rate is 4.4 Mbps.
{"title":"Hardware implementation of 128-bit symmetric cipher SEED","authors":"Young-ho Seo, Jong-Hyeon Kim, Dong-Wook Kim","doi":"10.1109/APASIC.2000.896939","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896939","url":null,"abstract":"This paper presents a hardware implementation of SEED, which is a Korean standard 128-bit symmetric block cipher: the target of the design was FPGA, but SEED was designed technology-independently for other applications such as ASIC or core-based designs. Hence in the case of changing the target of design, it is not necessary to modify design or to need minor modification in order to reuse the design. The design consists of round key generation part, F-function part, control part and round process part. Since SEED algorithm requires a lot of hardware resources, each unit was designed only once, except S-Box, and operated sequentially. Therefore the number of gates was minimized and SEED algorithm was fitted in FPGA without additional components. Also it was confirmed that the rate of resource usage is about 80% in ALTERA 10 KE. The design was synthesized in SYNOPSYS synthesis tool using ALTERA 10 K library and was simulated in MAX+PLUSII FPGA tool. The SEED design operates in a clock frequency of 5 MHz and uses 145 clocks. So encryption rate is 4.4 Mbps.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115685715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896978
H. Akita, S. Eto, K. Isobe, K. Tsuchida, H. Toda, T. Seki
A new architecture of the analog mirror type DLL has been developed. A dynamic comparator and self-calibration feedback loop are employed. The operation error of less than 50ps is confirmed under the condition of 1.6V supply voltage and 1.4V internal voltage. The proposed circuit is suitable for low-voltage and high-speed applications.
{"title":"A novel analog mirror type DLL suitable for low voltage operation with self-calibration method","authors":"H. Akita, S. Eto, K. Isobe, K. Tsuchida, H. Toda, T. Seki","doi":"10.1109/APASIC.2000.896978","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896978","url":null,"abstract":"A new architecture of the analog mirror type DLL has been developed. A dynamic comparator and self-calibration feedback loop are employed. The operation error of less than 50ps is confirmed under the condition of 1.6V supply voltage and 1.4V internal voltage. The proposed circuit is suitable for low-voltage and high-speed applications.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120963545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896920
F. Murabayashi, M. Matsumoto, K. Hanzawa, T. Yamauchi, K. Sakurai, H. Yamada, S. Shimada, A. Miyazaki
A programmable sensor signal conditioning LSI has a programmable interface circuit to input various signals and has a wide signal range from 10 mV to 2 V. The LSI can calibrate errors of various sensors transfer within 0.5% accuracy in a wide signal range. The signal conditioning LSI has three main modules, that is a sigma-delta AD-converter, a high reliability EPROM, and a 16 bit signal conditioning DSP. The sigma-delta AD-converter has a programmable interface and 10 /spl mu/V minimum resolution. Information determining the input signal range and calibration data are stored in a high reliability EPROM which has a redundant cell architecture. These modules have been integrated in a 0.8 /spl mu/m CMOS process and the chip is 4.3 mm/spl times/4.7 mm.
可编程传感器信号调理LSI具有可编程接口电路，用于输入各种信号，信号范围从10mv到2v。该LSI可在较宽的信号范围内校准各种传感器的误差，精度在0.5%以内。信号调理LSI有三个主要模块，即sigma-delta模数转换器、高可靠性EPROM和16位信号调理DSP。sigma-delta模数转换器具有可编程接口和10 /spl mu/V的最小分辨率。确定输入信号范围的信息和校准数据存储在具有冗余单元结构的高可靠性EPROM中。这些模块集成在0.8 /spl μ m CMOS工艺中，芯片尺寸为4.3 mm/spl倍/4.7 mm。
{"title":"A programmable sensor signal conditioning LSI","authors":"F. Murabayashi, M. Matsumoto, K. Hanzawa, T. Yamauchi, K. Sakurai, H. Yamada, S. Shimada, A. Miyazaki","doi":"10.1109/APASIC.2000.896920","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896920","url":null,"abstract":"A programmable sensor signal conditioning LSI has a programmable interface circuit to input various signals and has a wide signal range from 10 mV to 2 V. The LSI can calibrate errors of various sensors transfer within 0.5% accuracy in a wide signal range. The signal conditioning LSI has three main modules, that is a sigma-delta AD-converter, a high reliability EPROM, and a 16 bit signal conditioning DSP. The sigma-delta AD-converter has a programmable interface and 10 /spl mu/V minimum resolution. Information determining the input signal range and calibration data are stored in a high reliability EPROM which has a redundant cell architecture. These modules have been integrated in a 0.8 /spl mu/m CMOS process and the chip is 4.3 mm/spl times/4.7 mm.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"450 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125802365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896984
Y. Hirose, M. Saito, Hiroyuki Utsumi, Toshiaki Saruwatari, A. Suga, T. Sukemura, H. Takahashi, H. Miyake, Y. Takebe, M. Kimura, H. Okano, Masayuki Tsuji, T. Satoh, T. Katayama
A 4-way VLIW microprocessor based on an improved VLIW architecture is developed for embedded application in a 0.18 /spl mu/m 5-layer-metal CMOS process. This processor equips a 2-way integer pipeline and a 2-way floating/media pipeline. Each floating pipeline and media pipeline has 2-parallel and 4-parallel SIMD mechanisms, respectively. The processor equips separate instruction and data caches; each of 16 KB size and 4-way set associative. 6.7 M transistors are integrated in an area of 7.5 mm/spl times/7.5 mm. We also developed companion chip which is used together with the processor. Companion chip is fabricated using a 0.25 /spl mu/m 4-layer-metal CMOS process.
{"title":"A 4-way VLIW embedded processor and its companion chip","authors":"Y. Hirose, M. Saito, Hiroyuki Utsumi, Toshiaki Saruwatari, A. Suga, T. Sukemura, H. Takahashi, H. Miyake, Y. Takebe, M. Kimura, H. Okano, Masayuki Tsuji, T. Satoh, T. Katayama","doi":"10.1109/APASIC.2000.896984","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896984","url":null,"abstract":"A 4-way VLIW microprocessor based on an improved VLIW architecture is developed for embedded application in a 0.18 /spl mu/m 5-layer-metal CMOS process. This processor equips a 2-way integer pipeline and a 2-way floating/media pipeline. Each floating pipeline and media pipeline has 2-parallel and 4-parallel SIMD mechanisms, respectively. The processor equips separate instruction and data caches; each of 16 KB size and 4-way set associative. 6.7 M transistors are integrated in an area of 7.5 mm/spl times/7.5 mm. We also developed companion chip which is used together with the processor. Companion chip is fabricated using a 0.25 /spl mu/m 4-layer-metal CMOS process.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121426299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896903
Gwo-Jeng Yu, Bin-Da Liu, Chun-Yueh Huang
In this paper, we propose a current-mode multiple input maximum circuit with bi-directional operation, using 7n+10 transistors for n inputs. Owing to the single-stage architecture, the proposed circuit has the merits of high speed, high accuracy, and no accumulated errors. This circuit has been fabricated in 0.6 /spl mu/m CMOS technology, and the experimental result has verified the bidirectional maximum function of this circuit.
{"title":"Bi-directional current-mode multiple input maximum circuit","authors":"Gwo-Jeng Yu, Bin-Da Liu, Chun-Yueh Huang","doi":"10.1109/APASIC.2000.896903","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896903","url":null,"abstract":"In this paper, we propose a current-mode multiple input maximum circuit with bi-directional operation, using 7n+10 transistors for n inputs. Owing to the single-stage architecture, the proposed circuit has the merits of high speed, high accuracy, and no accumulated errors. This circuit has been fabricated in 0.6 /spl mu/m CMOS technology, and the experimental result has verified the bidirectional maximum function of this circuit.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116556376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896962
Ilseok Suh, Hong-Sik Kim, Sungho Kang, G. Han
The increase in integrity of the recent VLSI technology has enabled a trend of small and portable applications. These portable applications, like notebook computers and cellular phones, need the high-performance and low-power consumption. In most products the major power consuming elements are the memories. So low power memory technology has been developed. But the test features have not been studied sufficiently. This paper provides a test methodology useful for low power SRAM's. Also simulation results for the Driving Source Line technology show how useful the Iddq test is.
{"title":"Test methodology for low power SRAM's (Is Iddq test useful for low power SRAM's?)","authors":"Ilseok Suh, Hong-Sik Kim, Sungho Kang, G. Han","doi":"10.1109/APASIC.2000.896962","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896962","url":null,"abstract":"The increase in integrity of the recent VLSI technology has enabled a trend of small and portable applications. These portable applications, like notebook computers and cellular phones, need the high-performance and low-power consumption. In most products the major power consuming elements are the memories. So low power memory technology has been developed. But the test features have not been studied sufficiently. This paper provides a test methodology useful for low power SRAM's. Also simulation results for the Driving Source Line technology show how useful the Iddq test is.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125684952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896897
M. Hirata, Y. Suzuki, M. Yoshida, Y. Arayashiki, N. Sumiyoshi, A. Thanachayanont
In this paper, new plus- and minus-voltage generators for TFT-LCD panels utilizing charge pump circuits are proposed. The plus- and minus-voltage generators can generate voltages with any amplitude by simply changing the number of stages of the charge pump circuit. It is demonstrated that the proposed generators can provide enough plus or minus bias-voltage for TFT-LCD panels by using the circuit analysis program HSPICE.
{"title":"New plus- and minus-voltage generators for TFT-LCD panels","authors":"M. Hirata, Y. Suzuki, M. Yoshida, Y. Arayashiki, N. Sumiyoshi, A. Thanachayanont","doi":"10.1109/APASIC.2000.896897","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896897","url":null,"abstract":"In this paper, new plus- and minus-voltage generators for TFT-LCD panels utilizing charge pump circuits are proposed. The plus- and minus-voltage generators can generate voltages with any amplitude by simply changing the number of stages of the charge pump circuit. It is demonstrated that the proposed generators can provide enough plus or minus bias-voltage for TFT-LCD panels by using the circuit analysis program HSPICE.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115829728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896961
JaeHeung Park, Hoon Chang, Ohyoung Song
In this paper, we describe the implementation of BIST technique which is applied to enhance the reliability of the FLOVA chip i.e., the floating point DSP core for processing graphic data and 3D graphics. In order to enhance the reliability of FLOVA, we adopt the BIST technique for floating-point modules which have complicated logic. For embedded data and program memory, we adopt the memory BIST technique. The boundary scan technique, providing board-level testing and to control BIST logic, has been also implemented.
{"title":"An efficient implementation of BIST for floating point DSP processor","authors":"JaeHeung Park, Hoon Chang, Ohyoung Song","doi":"10.1109/APASIC.2000.896961","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896961","url":null,"abstract":"In this paper, we describe the implementation of BIST technique which is applied to enhance the reliability of the FLOVA chip i.e., the floating point DSP core for processing graphic data and 3D graphics. In order to enhance the reliability of FLOVA, we adopt the BIST technique for floating-point modules which have complicated logic. For embedded data and program memory, we adopt the memory BIST technique. The boundary scan technique, providing board-level testing and to control BIST logic, has been also implemented.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"45 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120979085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the log domain low-pass filter based on the MOSFET square law is proposed. This approach demonstrates that the cutoff frequency of the low-pass filter is not only attainable at megahertz frequencies but also tunable electronically. In addition, implemented by current-mode square-root circuit blocks, current mirrors and capacitors, the proposed low-pass filter can be operated with a 3.3 V power supply voltage. The proposed circuit has been simulated in 0.35 /spl mu/m CMOS technology, and the simulation results show that the proposed circuit has the merits of high frequency operation, tuneability, low power supply voltage operation.
{"title":"Design of log domain low-pass filters by MOSFET square law","authors":"Gwo-Jeng Yu, Bin-Da Liu, Yuan-Chia Hsu, Chun-Yueh Huang","doi":"10.1109/APASIC.2000.896895","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896895","url":null,"abstract":"In this paper, the log domain low-pass filter based on the MOSFET square law is proposed. This approach demonstrates that the cutoff frequency of the low-pass filter is not only attainable at megahertz frequencies but also tunable electronically. In addition, implemented by current-mode square-root circuit blocks, current mirrors and capacitors, the proposed low-pass filter can be operated with a 3.3 V power supply voltage. The proposed circuit has been simulated in 0.35 /spl mu/m CMOS technology, and the simulation results show that the proposed circuit has the merits of high frequency operation, tuneability, low power supply voltage operation.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128037743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896937
Y. Lim
This paper describes an efficient DES implementation that encrypts a 64-bit plain text block in 8 clock cycles. The 8 cycle processing latency optimizes the throughput of a pipelined DES system, where a byte-wide bus is used. Also, by decreasing the system clock frequency by a factor of 2, the switching power consumption is reduced compared to the conventional implementations. Our approach is based on the time multiplexed cipher function that requires only one copy of S-Box realization unlike other 8-cycle implementations.
{"title":"Efficient 8-cycle DES implementation","authors":"Y. Lim","doi":"10.1109/APASIC.2000.896937","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896937","url":null,"abstract":"This paper describes an efficient DES implementation that encrypts a 64-bit plain text block in 8 clock cycles. The 8 cycle processing latency optimizes the throughput of a pipelined DES system, where a byte-wide bus is used. Also, by decreasing the system clock frequency by a factor of 2, the switching power consumption is reduced compared to the conventional implementations. Our approach is based on the time multiplexed cipher function that requires only one copy of S-Box realization unlike other 8-cycle implementations.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"15 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132285696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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