Design of a Scalable Network of Communicating Soft Processors on FPGA

Abstract

In this work we investigate the implementation of a general parallel architecture using platform FPGA. With the implementation of communicating multiple soft processors mapped over a hypercube topology, our objective is to determine platform FPGA and SoC design environment advantages and limits for scalable multiple processors conception. We investigate the effect of communication system in FPGA devices, experimenting with different designs decisions. We present some performance results with the illustration of a parallel sort algorithm.