Hardware Implementation of Yolov4-tiny for Object Detection

Abstract

The high computational power of GPUs allowed for larger networks to be used in object detection applications. However, due to the huge power consumption and inefficiency when it comes to memory access and the number of bits used to represent the data, it is difficult to use them in embedded applications. Therefore, extensive research has been conducted to use FPGAs as a highly efficient substitute for GPUs to implement deep learning algorithms. As the scale and complexity of the algorithms keep increasing each year to improve their performance, it becomes even harder to implement such algorithms on an FPGA without reusing hardware resources. In this work, we implement Yolov4-tiny on a single FPGA by applying several resource sharing and optimization techniques. Our implementation shows a decrease in power consumption that ranges from 66% to 93.5% less power when compared to software. Moreover, less hardware resources and faster inference time is achieved. When comparing with the hardware implementation of networks with similar size, our design is 6.67 times faster and uses 62.5% less energy per image.