Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664961
Wassim Alexan, Mohamed ElBeltagy, Amr Aboshousha
The ever-increasing transmissions of multimedia over the Internet is requiring more advanced security schemes. This paper proposes a lightweight image encryption scheme that is based on 2 stages. The first stage incorporates the use of Rule 30 cellular automaton, while the second stage incorporates the use of a Lorenz system. Performance of the proposed encryption scheme is evaluated using a number of metrics. The computed values of the metrics indicate a comparable performance to counterpart schemes from the literature, at a very low cost of processing time. Such a trait indicates that the proposed image encryption scheme possesses potential for real-time image security applications.
{"title":"Lightweight Image Encryption: Cellular Automata and the Lorenz System","authors":"Wassim Alexan, Mohamed ElBeltagy, Amr Aboshousha","doi":"10.1109/ICM52667.2021.9664961","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664961","url":null,"abstract":"The ever-increasing transmissions of multimedia over the Internet is requiring more advanced security schemes. This paper proposes a lightweight image encryption scheme that is based on 2 stages. The first stage incorporates the use of Rule 30 cellular automaton, while the second stage incorporates the use of a Lorenz system. Performance of the proposed encryption scheme is evaluated using a number of metrics. The computed values of the metrics indicate a comparable performance to counterpart schemes from the literature, at a very low cost of processing time. Such a trait indicates that the proposed image encryption scheme possesses potential for real-time image security applications.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115376344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664946
Aleieldin Shamseldin, Hassan Soubra, Reham H. Elnabawy
Digital Signal Processors are microprocessing units specially designed for performing operations on signals while optimizing performance. Soft-core processors are fully implemented using a hardware description language and are synthesized using the programmable logic resources available in a Field Programmable Gate Array.The objective addressed in this paper is measuring the ability of soft-core processors in performing digital signal processing algorithms. This paper presents the implementation of some signal processing operations in the Nios II soft-core Reduced Instruction Set Computer based processor. The performance of these operations is then evaluated by ensuring proper execution of functions and benchmarked against the TMS320DM64x+ DSP by Texas Instruments.
{"title":"Performance of DSP operations implemented using a soft microprocessor: a case study based on Nios II","authors":"Aleieldin Shamseldin, Hassan Soubra, Reham H. Elnabawy","doi":"10.1109/ICM52667.2021.9664946","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664946","url":null,"abstract":"Digital Signal Processors are microprocessing units specially designed for performing operations on signals while optimizing performance. Soft-core processors are fully implemented using a hardware description language and are synthesized using the programmable logic resources available in a Field Programmable Gate Array.The objective addressed in this paper is measuring the ability of soft-core processors in performing digital signal processing algorithms. This paper presents the implementation of some signal processing operations in the Nios II soft-core Reduced Instruction Set Computer based processor. The performance of these operations is then evaluated by ensuring proper execution of functions and benchmarked against the TMS320DM64x+ DSP by Texas Instruments.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124455651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664938
Andrew Boutros, E. Nurvitadhi, Vaughn Betz
Artificial intelligence (AI) has become an essential component in modern datacenter applications. The high computational complexity of AI algorithms and the stringent latency constraints for datacenter workloads necessitate the use of efficient specialized AI accelerators. However, the rapid changes in state-of-the-art AI algorithms as well as their varying compute and memory demands challenge accelerator deployments in datacenters as a result of the much slower hardware development cycle. To this end, field-programmable gate arrays (FPGAs) offer the necessary adaptability along with the desired custom hardware efficiency. However, FPGA design is non-trivial; it requires deep hardware expertise and suffers from long compile and debug times, making FPGAs difficult to use for software-oriented AI application developers. AI inference soft processor overlays address this by allowing application developers to write their AI algorithms in a high-level programming language, which are then compiled into instructions to be executed on an AI-targeted soft processor implemented on the FPGA. While the generality of such overlays can eliminate the long bitstream compile times and make FPGAs more accessible for application developers, some classes of the target workloads do not fully utilize the overlay resources resulting in sub-optimal efficiency. In this paper, we investigate the trade-off between hardware efficiency and designer productivity by quantifying the gains and costs of specializing overlays for different classes of AI workloads. We show that per-workload specialized variants of the neural processing unit (NPU), a state-of-the-art AI inference overlay, can achieve up to 41% better performance and 44% area savings.
{"title":"Specializing for Efficiency: Customizing AI Inference Processors on FPGAs","authors":"Andrew Boutros, E. Nurvitadhi, Vaughn Betz","doi":"10.1109/ICM52667.2021.9664938","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664938","url":null,"abstract":"Artificial intelligence (AI) has become an essential component in modern datacenter applications. The high computational complexity of AI algorithms and the stringent latency constraints for datacenter workloads necessitate the use of efficient specialized AI accelerators. However, the rapid changes in state-of-the-art AI algorithms as well as their varying compute and memory demands challenge accelerator deployments in datacenters as a result of the much slower hardware development cycle. To this end, field-programmable gate arrays (FPGAs) offer the necessary adaptability along with the desired custom hardware efficiency. However, FPGA design is non-trivial; it requires deep hardware expertise and suffers from long compile and debug times, making FPGAs difficult to use for software-oriented AI application developers. AI inference soft processor overlays address this by allowing application developers to write their AI algorithms in a high-level programming language, which are then compiled into instructions to be executed on an AI-targeted soft processor implemented on the FPGA. While the generality of such overlays can eliminate the long bitstream compile times and make FPGAs more accessible for application developers, some classes of the target workloads do not fully utilize the overlay resources resulting in sub-optimal efficiency. In this paper, we investigate the trade-off between hardware efficiency and designer productivity by quantifying the gains and costs of specializing overlays for different classes of AI workloads. We show that per-workload specialized variants of the neural processing unit (NPU), a state-of-the-art AI inference overlay, can achieve up to 41% better performance and 44% area savings.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122230403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664934
Suvarna Mujumdar, Nelofer Afzal, S. Loan
In this work, we design and simulate a high performance Carbon Nanotube Field Effect Transistor (CNTFET) based current steering (CS) digital to analog-(DAC) circuit. The proposed DAC employs current steering technique with Simple Current Mirror, is a 4-bit with a sampling rate of 0.1G sample/sec, employing 32 nm technology node CNTFETs. A CS-DAC employing the conventional 32 technology node MOS has also been designed and compared with the proposed CNTFET based CS-DAC. The comparative analysis of various performance measuring parameters like integer non-linearity (INL), differential nonlinearity (DNL) glitch energy, power consumption etc. has been comprehensively performed. It has been observed that the unique properties of CNTs have made the proposed DAC to significantly outperform the conventional MOS technology based DAC. The static and dynamic performance of CS-DAC has been studied thoroughly at 0.9V power supply. It has been observed that in the proposed CNTFET based CS-DAC, INL and DNL have got decreased by 87.5% and 91.80% respectively in comparison to the conventional MOS based CS-DAC. Further, the dynamic performance measuring parameter like Spurious Free Dynamic Range (SFDR) has increased by 41.39 % and the power consumption has got decreased by ~53% in the proposed DAC in comparison to the conventional DAC. The glitch power in CNTFET based DAC has got reduced by 2.5 times in comparison to that in conventional DAC.
{"title":"A 4-bit Binary weighted Current Steering Digital To Analog Converter based on CNTFET","authors":"Suvarna Mujumdar, Nelofer Afzal, S. Loan","doi":"10.1109/ICM52667.2021.9664934","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664934","url":null,"abstract":"In this work, we design and simulate a high performance Carbon Nanotube Field Effect Transistor (CNTFET) based current steering (CS) digital to analog-(DAC) circuit. The proposed DAC employs current steering technique with Simple Current Mirror, is a 4-bit with a sampling rate of 0.1G sample/sec, employing 32 nm technology node CNTFETs. A CS-DAC employing the conventional 32 technology node MOS has also been designed and compared with the proposed CNTFET based CS-DAC. The comparative analysis of various performance measuring parameters like integer non-linearity (INL), differential nonlinearity (DNL) glitch energy, power consumption etc. has been comprehensively performed. It has been observed that the unique properties of CNTs have made the proposed DAC to significantly outperform the conventional MOS technology based DAC. The static and dynamic performance of CS-DAC has been studied thoroughly at 0.9V power supply. It has been observed that in the proposed CNTFET based CS-DAC, INL and DNL have got decreased by 87.5% and 91.80% respectively in comparison to the conventional MOS based CS-DAC. Further, the dynamic performance measuring parameter like Spurious Free Dynamic Range (SFDR) has increased by 41.39 % and the power consumption has got decreased by ~53% in the proposed DAC in comparison to the conventional DAC. The glitch power in CNTFET based DAC has got reduced by 2.5 times in comparison to that in conventional DAC.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131322611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664911
Amir R. Ali, A. Raouf, Amr Elnemr
recently, health monitoring of structures possesses great attention for various purposes. One of them follows the status of the existing structure, especially if it is an infrastructure that handles traffic load and mainstream of any country. Secondly, it lowers the cost of maintenance and rehabilitation as no human skills are required for testing existing structures and evaluating manuals. In addition, it lowers the budget cost for any existing structures and specifies exactly the required budget for repairing the defective parts in these structures. In this paper, two novel new techniques are suggested over monitoring the structures: external and internal. The techniques are mainly based on reading the deformation optically on the first technique, while the second technique exploits the measurement of the back electromotive force (back EMF voltages). The output voltages and deformation readings are reported for supported beams. From the analytical results, the resolution for the first technique is reported up to 0.2N, around 20 gm On the other hand, the second technique implied 31.25N, rendering around 3186.6gm The results show two orders of magnitudes enhancement when using the first technique, depending on the optical sensing element over the other one.
{"title":"Novel Sensors Design for SHM of RC Using the Opto-Mechatronics Technologies","authors":"Amir R. Ali, A. Raouf, Amr Elnemr","doi":"10.1109/ICM52667.2021.9664911","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664911","url":null,"abstract":"recently, health monitoring of structures possesses great attention for various purposes. One of them follows the status of the existing structure, especially if it is an infrastructure that handles traffic load and mainstream of any country. Secondly, it lowers the cost of maintenance and rehabilitation as no human skills are required for testing existing structures and evaluating manuals. In addition, it lowers the budget cost for any existing structures and specifies exactly the required budget for repairing the defective parts in these structures. In this paper, two novel new techniques are suggested over monitoring the structures: external and internal. The techniques are mainly based on reading the deformation optically on the first technique, while the second technique exploits the measurement of the back electromotive force (back EMF voltages). The output voltages and deformation readings are reported for supported beams. From the analytical results, the resolution for the first technique is reported up to 0.2N, around 20 gm On the other hand, the second technique implied 31.25N, rendering around 3186.6gm The results show two orders of magnitudes enhancement when using the first technique, depending on the optical sensing element over the other one.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"14 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128866800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664931
R. Islam, E. Abdel-Raheem, M. Tarique
This paper presents a cough sound-based fast, automated, and noninvasive COVID-19 detection system to discriminate the cough sounds of the COVID-19 patients from the healthy individuals. The proposed system extracts an acoustic feature called chromagram from the cough sound samples and applies it to the input of a classifier algorithm. Two artificial neural network (ANN) based classifiers namely convolutional neural network (CNN) and deep neural network (DNN) are modeled for this purpose. The simulation results show that the proposed system achieves an accuracy of 92.9% and 91.7% with CNN and DNN respectively. The performance comparison of the proposed system with two popular machine learning algorithms namely support vector machine (SVM) and k-nearest neighbor (kNN) are also presented in this work.
{"title":"Early Detection of COVID-19 Patients using Chromagram Features of Cough Sound Recordings with Machine Learning Algorithms","authors":"R. Islam, E. Abdel-Raheem, M. Tarique","doi":"10.1109/ICM52667.2021.9664931","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664931","url":null,"abstract":"This paper presents a cough sound-based fast, automated, and noninvasive COVID-19 detection system to discriminate the cough sounds of the COVID-19 patients from the healthy individuals. The proposed system extracts an acoustic feature called chromagram from the cough sound samples and applies it to the input of a classifier algorithm. Two artificial neural network (ANN) based classifiers namely convolutional neural network (CNN) and deep neural network (DNN) are modeled for this purpose. The simulation results show that the proposed system achieves an accuracy of 92.9% and 91.7% with CNN and DNN respectively. The performance comparison of the proposed system with two popular machine learning algorithms namely support vector machine (SVM) and k-nearest neighbor (kNN) are also presented in this work.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122313672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664936
Mohamed H. Abdelwahab, Hassan Mostafa, Ahmed M. Khattab
In this paper, a lightweight deep learning-based time series forecasting model is developed to predict the daily temperature values for one year ahead. The predictive model is an encoder-decoder model with a single LSTM layer for each of the encoder and decoder. Unlike the existing literature of time series forecasting, the proposed framework is designed to be lightweight to be deployed on low-complexity hardware platforms installed in the olive groves. Using real-life data of a Spanish olive grove, we show that the accuracy loss of the proposed lightweight framework is insignificant (0.004% to 0.06%). On the other hand, the implementation complexity of the proposed model is orders of magnitude lower than existing models, making it more suitable for implementation on embedded hardware platforms.
{"title":"A Lightweight Deep Learning Framework for Long-Term Weather Forecasting in Olive Precision Agriculture","authors":"Mohamed H. Abdelwahab, Hassan Mostafa, Ahmed M. Khattab","doi":"10.1109/ICM52667.2021.9664936","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664936","url":null,"abstract":"In this paper, a lightweight deep learning-based time series forecasting model is developed to predict the daily temperature values for one year ahead. The predictive model is an encoder-decoder model with a single LSTM layer for each of the encoder and decoder. Unlike the existing literature of time series forecasting, the proposed framework is designed to be lightweight to be deployed on low-complexity hardware platforms installed in the olive groves. Using real-life data of a Spanish olive grove, we show that the accuracy loss of the proposed lightweight framework is insignificant (0.004% to 0.06%). On the other hand, the implementation complexity of the proposed model is orders of magnitude lower than existing models, making it more suitable for implementation on embedded hardware platforms.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"69 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131602650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664897
Osama A. El-Sayed, Salma K. Fawzy, Shahd H. Tolba, Raghda S. Salem, Youssef S. Hassan, A. M. Ahmed, Ahmed K. F. Khattab
According to the increase in the number of Internet-connected devices in Intelligent Transport Systems (ITSs), the network traffic carried by ITSs has significantly increased. Consequently, the number of new security threats and attacks has increased beyond the ability of exiting systems to solve. New technologies have been recently used to address the emerging security challenges in ITSs such as the use of machine learning techniques to predict new attacks and threats. In this paper, we propose an effective solution for this problem using deep learning to detect and classify the attacks in the widely used UNSW-NB15 dataset. A discriminating feature of our work is the use of a reduced set of features (only 20 out of 49) in the proposed model. Our experimental results show that the proposed model achieves remarkable accuracy despite the use of a subset of carefully selected features in the UNSW-NB15 dataset.
{"title":"Deep Learning Framework for Accurate Network Intrusion Detection in ITSs","authors":"Osama A. El-Sayed, Salma K. Fawzy, Shahd H. Tolba, Raghda S. Salem, Youssef S. Hassan, A. M. Ahmed, Ahmed K. F. Khattab","doi":"10.1109/ICM52667.2021.9664897","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664897","url":null,"abstract":"According to the increase in the number of Internet-connected devices in Intelligent Transport Systems (ITSs), the network traffic carried by ITSs has significantly increased. Consequently, the number of new security threats and attacks has increased beyond the ability of exiting systems to solve. New technologies have been recently used to address the emerging security challenges in ITSs such as the use of machine learning techniques to predict new attacks and threats. In this paper, we propose an effective solution for this problem using deep learning to detect and classify the attacks in the widely used UNSW-NB15 dataset. A discriminating feature of our work is the use of a reduced set of features (only 20 out of 49) in the proposed model. Our experimental results show that the proposed model achieves remarkable accuracy despite the use of a subset of carefully selected features in the UNSW-NB15 dataset.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121750049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664903
M. Walid, Menna M. Elnaggar, W. Sayed, L. Said, A. Radwan
This paper compares the performance of four different chaotic systems in path planning for surveillance applications. The four investigated systems are Lorenz, Arneodo, Liu, and Chen. While the Lorenz system was employed in a similar application before, Arneodo, Liu, and Chen systems are newly introduced in this paper. A bounded-grid chaotic path planner is proposed based on the mirror mapping technique, which keeps the robot bounded in the terrain and prevents it from going outside. The effect of using different state variables of each chaotic system to control the motion angle of the robot is discussed and shown to have a significant impact on the robot’s performance. The obtained trajectory and several performance metrics show promising results of the chaotic path planner for the four systems.
{"title":"A Comparative Study of Different Chaotic Systems in Path Planning for Surveillance Applications","authors":"M. Walid, Menna M. Elnaggar, W. Sayed, L. Said, A. Radwan","doi":"10.1109/ICM52667.2021.9664903","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664903","url":null,"abstract":"This paper compares the performance of four different chaotic systems in path planning for surveillance applications. The four investigated systems are Lorenz, Arneodo, Liu, and Chen. While the Lorenz system was employed in a similar application before, Arneodo, Liu, and Chen systems are newly introduced in this paper. A bounded-grid chaotic path planner is proposed based on the mirror mapping technique, which keeps the robot bounded in the terrain and prevents it from going outside. The effect of using different state variables of each chaotic system to control the motion angle of the robot is discussed and shown to have a significant impact on the robot’s performance. The obtained trajectory and several performance metrics show promising results of the chaotic path planner for the four systems.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121850240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664902
Sameh Sherif, Y. Ghallab, M. El-Wakad, Y. Ismail
Micro electric impedance spectroscopy (µEIS), are very tiny devices that use fluid as a working medium in conjunction with biological cells to extract different electrical parameters. Many advantages can be provided by using these tiny microfluidic devices, such as portability, disposable, and high accuracy. Dielectric parameters of biological cells are one of the interesting parameters that can be extracted using µEIS. This computational study represents the modification for both systems the parallel facing electrodes and the Coplanar electrodes using two main features the number of electrodes and the sequence of the excitation signal. The main target of the study is to show the sensitivity of each configuration related to the cell positioning and how can overcome the cell positioning effect using a new excitation signal distribution method and the number of electrodes. The proposed design and simulation results enhance the response of the microfluidic system.
{"title":"Impedance Spectroscopy based on The Cell Trajectory and New Strategy to Enhance The Accuracy of The Detection in The Microfluidic System","authors":"Sameh Sherif, Y. Ghallab, M. El-Wakad, Y. Ismail","doi":"10.1109/ICM52667.2021.9664902","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664902","url":null,"abstract":"Micro electric impedance spectroscopy (µEIS), are very tiny devices that use fluid as a working medium in conjunction with biological cells to extract different electrical parameters. Many advantages can be provided by using these tiny microfluidic devices, such as portability, disposable, and high accuracy. Dielectric parameters of biological cells are one of the interesting parameters that can be extracted using µEIS. This computational study represents the modification for both systems the parallel facing electrodes and the Coplanar electrodes using two main features the number of electrodes and the sequence of the excitation signal. The main target of the study is to show the sensitivity of each configuration related to the cell positioning and how can overcome the cell positioning effect using a new excitation signal distribution method and the number of electrodes. The proposed design and simulation results enhance the response of the microfluidic system.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133737366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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