Investigation of new NV memory architectures for low duty-cycle embedded systems

Abstract

Processors in sensor nodes offer very deep sleep modes to save energy and to increase the battery lifetime with the disadvantage that the content of the volatile memory will be typically lost in these modes. The backup and restore of data from volatile to non-volatile memories is expensive regarding the energy budget. Emerging new memory technologies offer the opportunity for new memory layouts in such embedded processors, and possibly help to reduce the energy consumption in low-duty cycle application. In this work an energy estimation approach for low-duty-cycle applications is presented, which estimates the energy cost, based on memory operations only. With that approach various memory layouts based on new non-volatile memory architectures are compared against each other. It turns out that the use of the new NV memories is a massive gain for the lifetime of sensor nodes.