Andreas Karlsson, O. Andersson, J. Sparsø, J. Rodrigues
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引用次数: 6
Abstract
This paper proposes IR-drop reduction of sub-VT circuits by de-synchronization. The de-synchronization concept is briefly demonstrated and analyzed by a case study. Extensive IR-drop analysis' of various technology options of a 65 nm CMOS family demonstrate how the noise margins are reduced due to switching noise on the supply rails. It is shown that a de-synchronized implementation reduces severe voltage drops on the supply rails by approximately 50%, compared to a clocked design.
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