Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404326
Hsu-Yu Chang, J. Woo
Novel source pocket Si Tunnel field effect transistor (TFET) is successfully fabricated by laser annealing. It shows reduced threshold voltage, steep subthreshold swing (46mV/dec), excellent ION/IOFF ratio (>;107) and improved output characteristics due to dramatic reduction of tunneling resistance.
{"title":"Group IV TFETs for very low power applications","authors":"Hsu-Yu Chang, J. Woo","doi":"10.1109/SUBVT.2012.6404326","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404326","url":null,"abstract":"Novel source pocket Si Tunnel field effect transistor (TFET) is successfully fabricated by laser annealing. It shows reduced threshold voltage, steep subthreshold swing (46mV/dec), excellent ION/IOFF ratio (>;107) and improved output characteristics due to dramatic reduction of tunneling resistance.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120995156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404315
A. Shrivastava, B. Calhoun
This paper presents a model for DC-DC converters that is used to study power management techniques like dynamic voltage and frequency scaling (DVFS) etc. It accurately predicts the behavior of DC-DC converters of varying topologies across output voltage and load current and predicts the relative benefits of different power management options down to low voltage and current levels.
{"title":"Modeling DC-DC converter efficiency and power management in ultra low power systems","authors":"A. Shrivastava, B. Calhoun","doi":"10.1109/SUBVT.2012.6404315","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404315","url":null,"abstract":"This paper presents a model for DC-DC converters that is used to study power management techniques like dynamic voltage and frequency scaling (DVFS) etc. It accurately predicts the behavior of DC-DC converters of varying topologies across output voltage and load current and predicts the relative benefits of different power management options down to low voltage and current levels.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114860629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404308
B. Minch
In this paper, we present a simple low-voltage MOS cascode current mirror featuring a step response and an output voltage swing comparable to those of a simple mirror and and output resistance comparable to that of a stacked mirror. The proposed mirror operates with an input voltage of Vdiode+VDSsat and can operate on a minimum supply of Vdiode + 2VDSsat. We validate the proposed mirror with a combination of simulated and measured results from a circuit prototyped from transistor arrays fabricated in a 0.5-μm CMOS process through MOSIS.
{"title":"A simple low-voltage cascode current mirror with enhanced dynamic performance","authors":"B. Minch","doi":"10.1109/SUBVT.2012.6404308","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404308","url":null,"abstract":"In this paper, we present a simple low-voltage MOS cascode current mirror featuring a step response and an output voltage swing comparable to those of a simple mirror and and output resistance comparable to that of a stacked mirror. The proposed mirror operates with an input voltage of Vdiode+VDSsat and can operate on a minimum supply of Vdiode + 2VDSsat. We validate the proposed mirror with a combination of simulated and measured results from a circuit prototyped from transistor arrays fabricated in a 0.5-μm CMOS process through MOSIS.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131037847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404323
Jing Wang, Zhang-fa Liu
This paper presents a novel merged circuit which can be used in wireless transmitter. This circuit joins up-conversion mixer and voltage controlled oscillator (VCO) together. The block plays an important role in a transmitter. The design is single-end input and output which can be applied to a communication system with 50ohm antenna directly. The proposed design adopts current reuse and matching work reuse structures. This solution can reduce the use of passive devices efficiently, so as to reduce the area of chip. The circuit is designed with SMIC 0.18um RF CMOS technology. Simulation results shown that, under a 1.2V voltage supply, the DC power consumption of the whole circuit is only about 4.7mW, the max conversion gain is 7.8dB, the noise figure is less than 20dB with a frequency range from 880MHz to 920MHz, and the phase noise is lower than -124dBc/Hz with 1MHz offset the 900MHz center frequency.
{"title":"A merged up-conversion mixer-VCO based on current reuse","authors":"Jing Wang, Zhang-fa Liu","doi":"10.1109/SUBVT.2012.6404323","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404323","url":null,"abstract":"This paper presents a novel merged circuit which can be used in wireless transmitter. This circuit joins up-conversion mixer and voltage controlled oscillator (VCO) together. The block plays an important role in a transmitter. The design is single-end input and output which can be applied to a communication system with 50ohm antenna directly. The proposed design adopts current reuse and matching work reuse structures. This solution can reduce the use of passive devices efficiently, so as to reduce the area of chip. The circuit is designed with SMIC 0.18um RF CMOS technology. Simulation results shown that, under a 1.2V voltage supply, the DC power consumption of the whole circuit is only about 4.7mW, the max conversion gain is 7.8dB, the noise figure is less than 20dB with a frequency range from 880MHz to 920MHz, and the phase noise is lower than -124dBc/Hz with 1MHz offset the 900MHz center frequency.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130247616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404322
K. Mazumdar, M. Stan
The increasing popularity of DVFS (dynamic voltage frequency scaling) schemes for portable low power applications demands highly efficient on chip DC-DC converters. The primary aim of this work is to enable increased efficiency of on-chip DC-DC conversion for near-threshold operation of multi-core architectures. The main idea is to supply nominal (high) off-chip voltage to a multi-core processor where cores are then “voltage-stacked” to generate a near-threshold (low) voltage based on Kirchhoff's voltage law through charge recycling. However this implicit down-conversion can be affected by the current imbalance between the cores. A push-pull switched-capacitor regulator has been designed to keep the mid voltage close to the near-threshold value of half-Vdd. Stacked-voltage domain with its self-regulation capability combined with push-pull based switch capacitor regulator has shown an average efficiency of more than 90% for 2:1 down conversion with workload imbalance varying up to 50% of Iload.
{"title":"Charge recycling on-chip DC-DC conversion for near-threshold operation","authors":"K. Mazumdar, M. Stan","doi":"10.1109/SUBVT.2012.6404322","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404322","url":null,"abstract":"The increasing popularity of DVFS (dynamic voltage frequency scaling) schemes for portable low power applications demands highly efficient on chip DC-DC converters. The primary aim of this work is to enable increased efficiency of on-chip DC-DC conversion for near-threshold operation of multi-core architectures. The main idea is to supply nominal (high) off-chip voltage to a multi-core processor where cores are then “voltage-stacked” to generate a near-threshold (low) voltage based on Kirchhoff's voltage law through charge recycling. However this implicit down-conversion can be affected by the current imbalance between the cores. A push-pull switched-capacitor regulator has been designed to keep the mid voltage close to the near-threshold value of half-Vdd. Stacked-voltage domain with its self-regulation capability combined with push-pull based switch capacitor regulator has shown an average efficiency of more than 90% for 2:1 down conversion with workload imbalance varying up to 50% of Iload.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122332453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404303
Andreas Karlsson, O. Andersson, J. Sparsø, J. Rodrigues
This paper proposes IR-drop reduction of sub-VT circuits by de-synchronization. The de-synchronization concept is briefly demonstrated and analyzed by a case study. Extensive IR-drop analysis' of various technology options of a 65 nm CMOS family demonstrate how the noise margins are reduced due to switching noise on the supply rails. It is shown that a de-synchronized implementation reduces severe voltage drops on the supply rails by approximately 50%, compared to a clocked design.
{"title":"IR-drop reduction in sub-VT circuits by de-synchronization","authors":"Andreas Karlsson, O. Andersson, J. Sparsø, J. Rodrigues","doi":"10.1109/SUBVT.2012.6404303","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404303","url":null,"abstract":"This paper proposes IR-drop reduction of sub-VT circuits by de-synchronization. The de-synchronization concept is briefly demonstrated and analyzed by a case study. Extensive IR-drop analysis' of various technology options of a 65 nm CMOS family demonstrate how the noise margins are reduced due to switching noise on the supply rails. It is shown that a de-synchronized implementation reduces severe voltage drops on the supply rails by approximately 50%, compared to a clocked design.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114284025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404324
Jianying Zhao, Y. Ramadass, D. Buss, Jianguo Ma
Devices that harvest electrical energy from mechanical vibrations have the problem that the frequency of the source vibration is often not matched to the resonant frequency of the energy harvesting device. The source vibration may vary with time, and it may have a broad spectrum. Previous work has recognized that maximum output power can be obtained over a fairly broad spectrum using a tunable, complex reactive impedance at the output of the device. The present paper explores the bias-flip (BF) technique, along with other microelectronic techniques, to implement this tunable, complex reactive impedance.
{"title":"Microelectronic techniques for frequency tuning of piezo-electric energy harvesting devices","authors":"Jianying Zhao, Y. Ramadass, D. Buss, Jianguo Ma","doi":"10.1109/SUBVT.2012.6404324","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404324","url":null,"abstract":"Devices that harvest electrical energy from mechanical vibrations have the problem that the frequency of the source vibration is often not matched to the resonant frequency of the energy harvesting device. The source vibration may vary with time, and it may have a broad spectrum. Previous work has recognized that maximum output power can be obtained over a fairly broad spectrum using a tunable, complex reactive impedance at the output of the device. The present paper explores the bias-flip (BF) technique, along with other microelectronic techniques, to implement this tunable, complex reactive impedance.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"20 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133622528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404307
B. Senale-Rodriguez, Yeqing Lu, P. Fay, D. Jena, A. Seabaugh, H. Xing, L. Barboni, F. Silveira
In this paper we show that tunnel field effect transistors (TFETs) biased in the subthreshold region promise several advantages for low-power/high-frequency analog IC applications (e.g. GHz operation with sub-0.1 mW power consumption). Analytical and TCAD models for graphene nano-ribbon (GNR) and InAs/GaSb nanowire TFETs are employed, respectively, for the first time in subthreshold analog circuit examples using the gm/Id integrated circuit (IC) design technique. From comparison of these TFET technologies with traditional FETs it is observed that due to the higher currents per unit gate width at low voltage for TFETs, smaller, higher speed, and lower power analog circuits are enabled.
{"title":"Perspectives of TFETs for low power analog ICs","authors":"B. Senale-Rodriguez, Yeqing Lu, P. Fay, D. Jena, A. Seabaugh, H. Xing, L. Barboni, F. Silveira","doi":"10.1109/SUBVT.2012.6404307","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404307","url":null,"abstract":"In this paper we show that tunnel field effect transistors (TFETs) biased in the subthreshold region promise several advantages for low-power/high-frequency analog IC applications (e.g. GHz operation with sub-0.1 mW power consumption). Analytical and TCAD models for graphene nano-ribbon (GNR) and InAs/GaSb nanowire TFETs are employed, respectively, for the first time in subthreshold analog circuit examples using the gm/Id integrated circuit (IC) design technique. From comparison of these TFET technologies with traditional FETs it is observed that due to the higher currents per unit gate width at low voltage for TFETs, smaller, higher speed, and lower power analog circuits are enabled.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122651368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404313
Bo Liu, J. P. de Gyvez, M. Ashouei
In this paper, the authors extend their work on the balancing-based subthreshold cell sizing methodology. The libraries were benchmarked against a library tuned for super-threshold operation. Two sets of standard cells have been properly sized for operation at 0.3V, and further characterized at different voltages. A super-threshold 90 nm low power library was chosen as a reference library to compare timing, power and voltage scaling ability. The resented libraries show a 31% timing improvement at 0.3 V without area penalty over the conventional library. The comparison of libraries at different voltages shows that with respect to the super-threshold library, the presented library with only transistor channel width tuning has on average 10% better timing from 0.3 V to 1.2 V, and that this library with both transistor channel width and length tuning show timing improvements of 31.4% and 6.9% when the supply voltage increases from 0.3 V to 0.6 V, respectively.
{"title":"Library tuning for subthreshold operation","authors":"Bo Liu, J. P. de Gyvez, M. Ashouei","doi":"10.1109/SUBVT.2012.6404313","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404313","url":null,"abstract":"In this paper, the authors extend their work on the balancing-based subthreshold cell sizing methodology. The libraries were benchmarked against a library tuned for super-threshold operation. Two sets of standard cells have been properly sized for operation at 0.3V, and further characterized at different voltages. A super-threshold 90 nm low power library was chosen as a reference library to compare timing, power and voltage scaling ability. The resented libraries show a 31% timing improvement at 0.3 V without area penalty over the conventional library. The comparison of libraries at different voltages shows that with respect to the super-threshold library, the presented library with only transistor channel width tuning has on average 10% better timing from 0.3 V to 1.2 V, and that this library with both transistor channel width and length tuning show timing improvements of 31.4% and 6.9% when the supply voltage increases from 0.3 V to 0.6 V, respectively.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114901826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404299
P. Beshay, J. Bolus, T. Blalock, V. Chandra, B. Calhoun
Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times. In this paper, we propose a post fabrication technique that takes advantage of the typically detrimental bias temperature instability (BTI) aging effect to improve SRAM sense amplifier offset.
{"title":"SRAM sense amplifier offset cancellation using BTI stress","authors":"P. Beshay, J. Bolus, T. Blalock, V. Chandra, B. Calhoun","doi":"10.1109/SUBVT.2012.6404299","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404299","url":null,"abstract":"Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times. In this paper, we propose a post fabrication technique that takes advantage of the typically detrimental bias temperature instability (BTI) aging effect to improve SRAM sense amplifier offset.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124872210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：