Multiple attempt write strategy for low energy STT-RAM

Abstract

In this paper, we demonstrate an energy-reduction strategy that exploits the stochastic switching characteristics of STT-RAM write operation and propose a multiple-attempt write technique needed for it. In contrast to the traditional approach which uses the pulse that guarantees writes for all cells, the proposed technique uses multiple short pulses. Individually, these pulses result in high probability of write error therefore multiple attempts are made until a successful write for all bits. Average write energy is significantly reduced because the average write duration is far shorter than the worst-case duration. We developed a self-validation write circuit that allows bit-wise validation and current de-activation without adding energy and area overhead. We evaluated the proposed circuit using a compact STT-RAM model targeting an implementation in a 10nm technology node. Results indicate that the proposed architecture reduces write energy by 94.6% compared to the conventional design. Compared to the best previously known architectures that rely on write-read-verify strategy we reduce write energy by 2.1x without area overhead.