Partial reset methodologies for improving random-pattern testability and BIST of sequential circuits

Abstract

The use of partial reset has been shown to have significant impact on test generation in a stored-pattern test application environment for sequential circuits. In this paper, we explore the use of partial reset in fault-independent testing and its application to built-in self-test of nonscan sequential circuits. Switching activities of circuit nodes coupled with the node interconnection structure is used to select a subset of the circuit flip-flops to be reset to logic 0 or logic 1 during test application. An average improvement of 15% in fault-coverage is obtained for circuits resistant to random pattern testing over existing full reset methods. We also present a technique to insert observable test points based on activity propagation analysis. With the combined partial reset and observable test point insertion methodologies, high fault coverages were obtained for most of our benchmark circuits.