Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646618
I. Pomeranz, S. Reddy
We study storage schemes for test patterns and test responses of combinational and synchronous sequential circuits which are tested off-line by a tester. These storage schemes provide new objectives for test compaction beyond the need to reduce the test set size as much as possible. We report on several postprocessing methods to reduce the storage requirements of a given test set and present experimental evidence pointing to the possibility of reducing the storage requirements by using appropriate compaction objectives during test generation.
{"title":"On test compaction objectives for combinational and sequential circuits","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ICVD.1998.646618","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646618","url":null,"abstract":"We study storage schemes for test patterns and test responses of combinational and synchronous sequential circuits which are tested off-line by a tester. These storage schemes provide new objectives for test compaction beyond the need to reduce the test set size as much as possible. We report on several postprocessing methods to reduce the storage requirements of a given test set and present experimental evidence pointing to the possibility of reducing the storage requirements by using appropriate compaction objectives during test generation.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115469257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646569
R. Brodersen
The InfoPad project was started at UC Berkeley in 1992 to investigate the issues involved in providing multimedia information access using a portable, wireless terminal. It quickly became clear that a key design constraint was the energy consumption, which could best be addressed through an integrated system approach. The project was therefore organized to address all design levels, including the applications and user interface, backbone network protocols, software for distributed network support, the wireless link, and the pad itself which used a number of low voltage ASIC designs and a processor running embedded code. Tools were developed when not available (particularly in support of low energy design), as well as an interface to mechanical designers who created a custom injection molded case. The wide scope of the project presented a number of unique challenges for a research environment and the lessons learnt are presented.
{"title":"The InfoPad project: review and lessons learned","authors":"R. Brodersen","doi":"10.1109/ICVD.1998.646569","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646569","url":null,"abstract":"The InfoPad project was started at UC Berkeley in 1992 to investigate the issues involved in providing multimedia information access using a portable, wireless terminal. It quickly became clear that a key design constraint was the energy consumption, which could best be addressed through an integrated system approach. The project was therefore organized to address all design levels, including the applications and user interface, backbone network protocols, software for distributed network support, the wireless link, and the pad itself which used a number of low voltage ASIC designs and a processor running embedded code. Tools were developed when not available (particularly in support of low energy design), as well as an interface to mechanical designers who created a custom injection molded case. The wide scope of the project presented a number of unique challenges for a research environment and the lessons learnt are presented.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125281792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646617
S. Yadavalli, Sanjay Sengupta
Automatic Test Pattern Generation (ATPG) for state-of-the-art commercial grade circuits is far more complex and requires much more engineering than for the ISCAS benchmark circuits. One among the several reasons for this increased complexity is the presence of embedded memories or register arrays in the circuit. Most ATPG research has focussed solely on algorithmic techniques for test generation disregarding much of the engineering aspects required to make automatic test generation a commercial reality. While commercial ATPG tools have provides memory simple primitives to model memories, a significant amount of expertise, research and design rule checking is required to utilize the ATPG provided primitives to usefully model memories and obtain substantial amounts of additional fault-coverage in a true partial scan industrial design of considerable size. In this paper we discuss a memory modeling methodology that shows promise and we present results to show its effectiveness in terms of increased fault-coverage.
{"title":"Impact and cost of modeling memories for ATPG for partial scan designs","authors":"S. Yadavalli, Sanjay Sengupta","doi":"10.1109/ICVD.1998.646617","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646617","url":null,"abstract":"Automatic Test Pattern Generation (ATPG) for state-of-the-art commercial grade circuits is far more complex and requires much more engineering than for the ISCAS benchmark circuits. One among the several reasons for this increased complexity is the presence of embedded memories or register arrays in the circuit. Most ATPG research has focussed solely on algorithmic techniques for test generation disregarding much of the engineering aspects required to make automatic test generation a commercial reality. While commercial ATPG tools have provides memory simple primitives to model memories, a significant amount of expertise, research and design rule checking is required to utilize the ATPG provided primitives to usefully model memories and obtain substantial amounts of additional fault-coverage in a true partial scan industrial design of considerable size. In this paper we discuss a memory modeling methodology that shows promise and we present results to show its effectiveness in terms of increased fault-coverage.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126874249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646602
H. Nguyen, R. Roy, A. Chatterjee
The use of partial reset has been shown to have significant impact on test generation in a stored-pattern test application environment for sequential circuits. In this paper, we explore the use of partial reset in fault-independent testing and its application to built-in self-test of nonscan sequential circuits. Switching activities of circuit nodes coupled with the node interconnection structure is used to select a subset of the circuit flip-flops to be reset to logic 0 or logic 1 during test application. An average improvement of 15% in fault-coverage is obtained for circuits resistant to random pattern testing over existing full reset methods. We also present a technique to insert observable test points based on activity propagation analysis. With the combined partial reset and observable test point insertion methodologies, high fault coverages were obtained for most of our benchmark circuits.
{"title":"Partial reset methodologies for improving random-pattern testability and BIST of sequential circuits","authors":"H. Nguyen, R. Roy, A. Chatterjee","doi":"10.1109/ICVD.1998.646602","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646602","url":null,"abstract":"The use of partial reset has been shown to have significant impact on test generation in a stored-pattern test application environment for sequential circuits. In this paper, we explore the use of partial reset in fault-independent testing and its application to built-in self-test of nonscan sequential circuits. Switching activities of circuit nodes coupled with the node interconnection structure is used to select a subset of the circuit flip-flops to be reset to logic 0 or logic 1 during test application. An average improvement of 15% in fault-coverage is obtained for circuits resistant to random pattern testing over existing full reset methods. We also present a technique to insert observable test points based on activity propagation analysis. With the combined partial reset and observable test point insertion methodologies, high fault coverages were obtained for most of our benchmark circuits.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114291280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646626
B. Laurent, G. Bosco, G. Saucier
In this paper, classical adder and multiplier architectures applied to the Xilinx XC5200 FPGA are compared. To inherit advantages of both structural and algorithmic approaches, hybrid solutions are proposed such that the optimal trade-off between architectures and technology is reached. The resulting schemes yield optimized performance after the use of Xilinx place and route tools.
{"title":"Fast arithmetic on Xilinx 5200 FPGA","authors":"B. Laurent, G. Bosco, G. Saucier","doi":"10.1109/ICVD.1998.646626","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646626","url":null,"abstract":"In this paper, classical adder and multiplier architectures applied to the Xilinx XC5200 FPGA are compared. To inherit advantages of both structural and algorithmic approaches, hybrid solutions are proposed such that the optimal trade-off between architectures and technology is reached. The resulting schemes yield optimized performance after the use of Xilinx place and route tools.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117005595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646620
D. Bhavsar
This paper presents a novel method for using the industry standard IEEE Std. 1149.1 test port for accessing chip-wide testability features. The scheme reconfigures the test port to switch its normal asynchronous-to-chip-logic operating mode to a special synchronous-to-chip-logic operating mode that can be exploited in chip-alone test environments. The method allows the internal testability features to be designed normally and operated at full speed in chip's native clock domain.
{"title":"A method for synchronizing IEEE 1149.1 test access port for chip level testability access","authors":"D. Bhavsar","doi":"10.1109/ICVD.1998.646620","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646620","url":null,"abstract":"This paper presents a novel method for using the industry standard IEEE Std. 1149.1 test port for accessing chip-wide testability features. The scheme reconfigures the test port to switch its normal asynchronous-to-chip-logic operating mode to a special synchronous-to-chip-logic operating mode that can be exploited in chip-alone test environments. The method allows the internal testability features to be designed normally and operated at full speed in chip's native clock domain.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130451522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646659
S. Chattopadhyay, P. P. Chaudhuri
Current renewed emphasis for more aggressive logic designs with lesser area, delay, and power, demands exploration of alternative avenues that would lead to better designs, may be at the higher cost of computation. This paper explores the avenue of the Genetic Algorithm (GA) for a holistic view for synthesis of Finite State Machine (FSM). Two aspects-state assignment and choice of sequential elements-significantly affect the cost of the combinational logic synthesized for a FSM. While the state assignment strategies reported in the literature target a specific type of sequential element (generally, a D flip-flop), this paper chooses a combination of available flip-flops to yield the best result. Thus the problems of state assignment and flip-flop selection have been integrated into a single genetic algorithmic formulation. Exhaustive experimentation done on a large suite of benchmarks have established the fact that on the average this tool outperforms the two level state assignment algorithm NOVA by more than 300%. The quality of the solution obtained and the high rate of convergence has established the effectiveness of the GA in solving this particular NP-complete problem. Further, the inherent parallelism of GA makes the proposed scheme ideal for solving the problem in a multiprocessor environment.
{"title":"Genetic algorithm based approach for integrated state assignment and flipflop selection in finite state machine synthesis","authors":"S. Chattopadhyay, P. P. Chaudhuri","doi":"10.1109/ICVD.1998.646659","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646659","url":null,"abstract":"Current renewed emphasis for more aggressive logic designs with lesser area, delay, and power, demands exploration of alternative avenues that would lead to better designs, may be at the higher cost of computation. This paper explores the avenue of the Genetic Algorithm (GA) for a holistic view for synthesis of Finite State Machine (FSM). Two aspects-state assignment and choice of sequential elements-significantly affect the cost of the combinational logic synthesized for a FSM. While the state assignment strategies reported in the literature target a specific type of sequential element (generally, a D flip-flop), this paper chooses a combination of available flip-flops to yield the best result. Thus the problems of state assignment and flip-flop selection have been integrated into a single genetic algorithmic formulation. Exhaustive experimentation done on a large suite of benchmarks have established the fact that on the average this tool outperforms the two level state assignment algorithm NOVA by more than 300%. The quality of the solution obtained and the high rate of convergence has established the effectiveness of the GA in solving this particular NP-complete problem. Further, the inherent parallelism of GA makes the proposed scheme ideal for solving the problem in a multiprocessor environment.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133897051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646627
S. Misra, R. Kolagotla, H. Srinivas, J. C. Mo, M. Diamondstein
We describe the VLSI implementation of a fully testable high-speed binary synchronous counter that is pre-loadable and auto-reloadable. High-speed operation is achieved by precomputing the carry independent terms and by using the carry signal as a selector in the last gate before the storage latch. An efficient test logic is used that has minimal impact on the counter speed during normal operation, and significantly reduces the test time and test cost.
{"title":"VLSI implementation of a 300-MHz 0.35-/spl mu/m CMOS 32-bit auto-reloadable binary synchronous counter with optimal test overhead delay","authors":"S. Misra, R. Kolagotla, H. Srinivas, J. C. Mo, M. Diamondstein","doi":"10.1109/ICVD.1998.646627","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646627","url":null,"abstract":"We describe the VLSI implementation of a fully testable high-speed binary synchronous counter that is pre-loadable and auto-reloadable. High-speed operation is achieved by precomputing the carry independent terms and by using the carry signal as a selector in the last gate before the storage latch. An efficient test logic is used that has minimal impact on the counter speed during normal operation, and significantly reduces the test time and test cost.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133866071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646581
N. Weste, D. Skellern, T. Percival
This paper summarizes development of a high-speed wireless local area network (WLAN) aimed at providing mobile multi-path resistant communications in excess of 25 Mbps at 5 GHz.
{"title":"Broadband U-NII wireless data","authors":"N. Weste, D. Skellern, T. Percival","doi":"10.1109/ICVD.1998.646581","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646581","url":null,"abstract":"This paper summarizes development of a high-speed wireless local area network (WLAN) aimed at providing mobile multi-path resistant communications in excess of 25 Mbps at 5 GHz.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129394504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646583
A. Basu, Raj S. Mitra, P. Marwedel
In embedded systems, programmable peripherals are often coupled with the main programmable processor to achieve the desired functionality. Interfacing such peripherals with the processor qualifies as an important task of hardware software codesign. In this paper, three important aspects of such interfacing, namely, the allocation of addresses to the devices, allocation of device drivers, and approaches to handle events and transitions have been discussed. The proposed approaches have been incorporated in a codesign system MICKEY. The paper includes a number of examples, taken from results synthesized by MICKEY, to illustrate the ideas.
{"title":"Interface synthesis for embedded applications in a codesign environment","authors":"A. Basu, Raj S. Mitra, P. Marwedel","doi":"10.1109/ICVD.1998.646583","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646583","url":null,"abstract":"In embedded systems, programmable peripherals are often coupled with the main programmable processor to achieve the desired functionality. Interfacing such peripherals with the processor qualifies as an important task of hardware software codesign. In this paper, three important aspects of such interfacing, namely, the allocation of addresses to the devices, allocation of device drivers, and approaches to handle events and transitions have been discussed. The proposed approaches have been incorporated in a codesign system MICKEY. The paper includes a number of examples, taken from results synthesized by MICKEY, to illustrate the ideas.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130765341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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