{"title":"Configurable architecture for memory BIST","authors":"A. Lotfi, P. Kabiri, Z. Navabi","doi":"10.1109/EWDTS.2011.6116571","DOIUrl":null,"url":null,"abstract":"The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different sizes and configurations with an arbitrary test algorithm is proposed.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 9th East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2011.6116571","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different sizes and configurations with an arbitrary test algorithm is proposed.
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