Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116408
V. Hahanov, A. Mischenko, S. Chumachenko, A. Hahanova, A. Priymak
The theory, methods and the architecture of parallel information's analysis is presented by the form of analytical, graph and table forms of associative relations for the search, recognition, diagnosis of destructive components and the decision making in n-dimensional vector cybernetic individual space. Vector -logical processes-models of actual oriented tasks are considered. They include the diagnostic of spam and the recovery of serviceability, the hardware-software components of computer systems and the decision quality is estimated by the interactions of non-arithmetic metrics of Boolean vectors. The concept of self-development information of computer ecosystem is offered. It repeats the evolution of the functionality of the person. Original processes-models of associative-logical information analysis are represented on the basis of high-speed multiprocessor in n-dimensional vector discrete space.
{"title":"Spam diagnosis infrastructure for individual cyberspace","authors":"V. Hahanov, A. Mischenko, S. Chumachenko, A. Hahanova, A. Priymak","doi":"10.1109/EWDTS.2011.6116408","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116408","url":null,"abstract":"The theory, methods and the architecture of parallel information's analysis is presented by the form of analytical, graph and table forms of associative relations for the search, recognition, diagnosis of destructive components and the decision making in n-dimensional vector cybernetic individual space. Vector -logical processes-models of actual oriented tasks are considered. They include the diagnostic of spam and the recovery of serviceability, the hardware-software components of computer systems and the decision quality is estimated by the interactions of non-arithmetic metrics of Boolean vectors. The concept of self-development information of computer ecosystem is offered. It repeats the evolution of the functionality of the person. Original processes-models of associative-logical information analysis are represented on the basis of high-speed multiprocessor in n-dimensional vector discrete space.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117233394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116419
H. F. Ugurdag, O. Keskin, Cihan Tunc, F. Temizkan, G. Fici, Soner Dedeoglu
Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are employed such as building fast multipliers. Most fast multiplier architectures use some form of a Carry Save Adder (CSA) Tree, which is also called Column Compression (CC). We propose a new CC method called RoCoCo (Row and Column Compression), which also compresses the tree along rows so that the final adder is small and fast. Although CC results in faster multipliers in ASIC implementations, it is an assumption by designers that they are not the wisest choice on FPGAs. On the contrary, we were able to show through Xilinx synthesis results that RoCoCo (and sometimes Dadda CC) frequently offer faster multipliers than the built-in implementation of the multiply operation in Xilinx ISE synthesis tool.
{"title":"RoCoCo: Row and Column Compression for high-performance multiplication on FPGAs","authors":"H. F. Ugurdag, O. Keskin, Cihan Tunc, F. Temizkan, G. Fici, Soner Dedeoglu","doi":"10.1109/EWDTS.2011.6116419","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116419","url":null,"abstract":"Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are employed such as building fast multipliers. Most fast multiplier architectures use some form of a Carry Save Adder (CSA) Tree, which is also called Column Compression (CC). We propose a new CC method called RoCoCo (Row and Column Compression), which also compresses the tree along rows so that the final adder is small and fast. Although CC results in faster multipliers in ASIC implementations, it is an assumption by designers that they are not the wisest choice on FPGAs. On the contrary, we were able to show through Xilinx synthesis results that RoCoCo (and sometimes Dadda CC) frequently offer faster multipliers than the built-in implementation of the multiply operation in Xilinx ISE synthesis tool.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125375698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116585
N. Khairova, N. Sharonova
In existing systems of machine translation the quality of automatic translation depends on mistakes of morphological, syntactic and semantic processing. The mistakes are mostly caused by mistakes of semantic processing and in particular by a wrong choice of a translation equivalent of polysemantic words. The article suggests a model of a logical net of relations of translation equivalents of polysemantic words in superphrasal unities. Finite predicates are used to build the network. Every polysemantic lexeme, sentence, idioglossary are designated by means of subject variables. Their meanings are determined by the predicate of object identification by means of a given variable. The logical network under consideration allows defining the meaning of a translation equivalent using the meanings of the previous polysemantic words in superphrasal unities.
{"title":"Modeling a logical network of relations of semantic items in superphrasal unities","authors":"N. Khairova, N. Sharonova","doi":"10.1109/EWDTS.2011.6116585","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116585","url":null,"abstract":"In existing systems of machine translation the quality of automatic translation depends on mistakes of morphological, syntactic and semantic processing. The mistakes are mostly caused by mistakes of semantic processing and in particular by a wrong choice of a translation equivalent of polysemantic words. The article suggests a model of a logical net of relations of translation equivalents of polysemantic words in superphrasal unities. Finite predicates are used to build the network. Every polysemantic lexeme, sentence, idioglossary are designated by means of subject variables. Their meanings are determined by the predicate of object identification by means of a given variable. The logical network under consideration allows defining the meaning of a translation equivalent using the meanings of the previous polysemantic words in superphrasal unities.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125998883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116423
V. Hahanov, K. Mostova, O. Paschenko
In this paper HW/SW systems testing and faults diagnosing approach is described, also method for effective faults detection and defects localization within the system-under-test is proposed.
本文阐述了软硬件系统的测试与故障诊断方法，并提出了在被测系统内部进行有效故障检测和缺陷定位的方法。
{"title":"Infrastructure for testing and diagnosing multimedia devices","authors":"V. Hahanov, K. Mostova, O. Paschenko","doi":"10.1109/EWDTS.2011.6116423","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116423","url":null,"abstract":"In this paper HW/SW systems testing and faults diagnosing approach is described, also method for effective faults detection and defects localization within the system-under-test is proposed.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132119276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116583
A. Chemeris, S. Reznikova
The representation of digital circuits that are designed by Boolean functions is considered. The syntax of Boolean function we use is presented. This digital circuit representation in the form of data-flow graph is used as a basis for parallelizing of simulation process for multiprocessor computers.
{"title":"Parallelizing of Boolean function system for device simulation","authors":"A. Chemeris, S. Reznikova","doi":"10.1109/EWDTS.2011.6116583","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116583","url":null,"abstract":"The representation of digital circuits that are designed by Boolean functions is considered. The syntax of Boolean function we use is presented. This digital circuit representation in the form of data-flow graph is used as a basis for parallelizing of simulation process for multiprocessor computers.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128871483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116597
A. Adamov, V. Hahanov
This paper describes a security model for protection of individual cyberspace (ICS) as a way of ensuring a secured user's virtual environment. A concept of cyberspace and its main definitions is determined, as well as a formal model that describes mapping of prototypes in cyberspace into real-world objects. Based on analysis of contemporary security threats and methods of protection against them basic requirements for a security model were declared to ensure availability, integrity and confidentiality of user data within cyberspace. Information on cyber threats, as well as a review of existing security solutions in cloud computing was taken as a basis for the proposed ICS security model. The goal of the paper is to represent an analysis of security issues related to ICS and propose the conceptual model of a modern security environment.
{"title":"A security model of individual cyberspace","authors":"A. Adamov, V. Hahanov","doi":"10.1109/EWDTS.2011.6116597","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116597","url":null,"abstract":"This paper describes a security model for protection of individual cyberspace (ICS) as a way of ensuring a secured user's virtual environment. A concept of cyberspace and its main definitions is determined, as well as a formal model that describes mapping of prototypes in cyberspace into real-world objects. Based on analysis of contemporary security threats and methods of protection against them basic requirements for a security model were declared to ensure availability, integrity and confidentiality of user data within cyberspace. Information on cyber threats, as well as a review of existing security solutions in cloud computing was taken as a basis for the proposed ICS security model. The goal of the paper is to represent an analysis of security issues related to ICS and propose the conceptual model of a modern security environment.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115944159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116601
Taavi Viilukas, M. Jenihhin, J. Raik, R. Ubar, S. Baranov
The paper presents an approach for integration of automatic test bench generation based on a hierarchical test pattern generator Decider into the high-level synthesis flow Abelite. While the high-level synthesis flow provides fast results of complex systems design, functional verification of the design including initial specification has remained until now a sophisticated manual process. The automatically generated test benches provide high code coverage for simulation and are readable for debug. The experiments demonstrate viability and efficiency of the proposed approach.
{"title":"Automated test bench generation for high-level synthesis flow ABELITE","authors":"Taavi Viilukas, M. Jenihhin, J. Raik, R. Ubar, S. Baranov","doi":"10.1109/EWDTS.2011.6116601","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116601","url":null,"abstract":"The paper presents an approach for integration of automatic test bench generation based on a hierarchical test pattern generator Decider into the high-level synthesis flow Abelite. While the high-level synthesis flow provides fast results of complex systems design, functional verification of the design including initial specification has remained until now a sophisticated manual process. The automatically generated test benches provide high code coverage for simulation and are readable for debug. The experiments demonstrate viability and efficiency of the proposed approach.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130698577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116426
G. Krivoulya, A. Shkil, D. Kucherenko
In this paper the issue of the computer systems users' competence analysis as one of its failing causes was considered. For this purpose the competence model for the analysis of witch it is necessary to carry out the diagnostic experiments, where the qualifying tasks will be open form tasks with a detailed answer, was proposed. In order to evaluate these tasks the mathematical apparatus of fuzzy logic was proposed to use. In this paper a justification of the operating fuzzy inference algorithm was given, and the model of condition-action rules composition was proposed.
{"title":"Competence as a support factor of the computer system operation","authors":"G. Krivoulya, A. Shkil, D. Kucherenko","doi":"10.1109/EWDTS.2011.6116426","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116426","url":null,"abstract":"In this paper the issue of the computer systems users' competence analysis as one of its failing causes was considered. For this purpose the competence model for the analysis of witch it is necessary to carry out the diagnostic experiments, where the qualifying tasks will be open form tasks with a detailed answer, was proposed. In order to evaluate these tasks the mathematical apparatus of fuzzy logic was proposed to use. In this paper a justification of the operating fuzzy inference algorithm was given, and the model of condition-action rules composition was proposed.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130837118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116425
T. Yves, V. Hahanov, Omar Alnahhal, Mikhail Maksimov, Dmitry Shcherbin, D. Yudin
This article describes an infrastructure and technologies for diagnosis. A transactional graph model and method for diagnosis of digital system-on-chip are developed. They are focused to considerable decrease the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations in the form of test, monitor, and functional component. The following problems are solved: creation of digital system model in the form of transaction graph and multitree of fault detection tables, as well as ternary matrices for activating functional components in tests, relative to the selected set of monitors; development of a method for analyzing the activation matrix to detect the faults with given depth and synthesizing logic functions for subsequent embedded hardware fault diagnosing.
{"title":"Diagnosis infrastructure of software-hardware systems","authors":"T. Yves, V. Hahanov, Omar Alnahhal, Mikhail Maksimov, Dmitry Shcherbin, D. Yudin","doi":"10.1109/EWDTS.2011.6116425","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116425","url":null,"abstract":"This article describes an infrastructure and technologies for diagnosis. A transactional graph model and method for diagnosis of digital system-on-chip are developed. They are focused to considerable decrease the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations in the form of test, monitor, and functional component. The following problems are solved: creation of digital system model in the form of transaction graph and multitree of fault detection tables, as well as ternary matrices for activating functional components in tests, relative to the selected set of monitors; development of a method for analyzing the activation matrix to detect the faults with given depth and synthesizing logic functions for subsequent embedded hardware fault diagnosing.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123269299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116609
Jiri Jenícek, O. Novák, Martin Chloupek
The paper deals with the problem of test data volume, decompressor hardware overhead and test application time of scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction and low decompressor hardware requirements. This paper presents an improved chain configuration method that enables both the test pattern overlapping technique and the test pattern broadcasting technique makes more efficiently. This new technique reduces substantially the number of conflicting bits in previously published scan chain reordering methods.
{"title":"Advanced scan chain configuration method for broadcast decompressor architecture","authors":"Jiri Jenícek, O. Novák, Martin Chloupek","doi":"10.1109/EWDTS.2011.6116609","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116609","url":null,"abstract":"The paper deals with the problem of test data volume, decompressor hardware overhead and test application time of scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction and low decompressor hardware requirements. This paper presents an improved chain configuration method that enables both the test pattern overlapping technique and the test pattern broadcasting technique makes more efficiently. This new technique reduces substantially the number of conflicting bits in previously published scan chain reordering methods.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126102327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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