C. Shung, R. Jain, K. Rimey, Edward Wang, M. Srivastava, B. Richards, E. Lettang, S. K. Azim, L. Thon, P. Hilfinger, J. Rabaey, R. Brodersen
{"title":"An integrated CAD system for algorithm-specific IC design","authors":"C. Shung, R. Jain, K. Rimey, Edward Wang, M. Srivastava, B. Richards, E. Lettang, S. K. Azim, L. Thon, P. Hilfinger, J. Rabaey, R. Brodersen","doi":"10.1109/HICSS.1989.47146","DOIUrl":null,"url":null,"abstract":"Lager, an integrated CAD (computer-aided design) system for algorithm-specific IC design, is described. It consists of a behavioral mapper and a silicon assembler. To generate a chip from a behavioral description, the user specifies both the behavioral description and a parameterized structural description. The behavior is mapped onto the parameterized structure to produce microcode and parameter values. The silicon assembler then translates the fill-out structural description into a physical layout. A number of algorithm-specific ICs designed with Lager have been fabricated and tested. A robot-control chip is described.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"115","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HICSS.1989.47146","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 115
Abstract
Lager, an integrated CAD (computer-aided design) system for algorithm-specific IC design, is described. It consists of a behavioral mapper and a silicon assembler. To generate a chip from a behavioral description, the user specifies both the behavioral description and a parameterized structural description. The behavior is mapped onto the parameterized structure to produce microcode and parameter values. The silicon assembler then translates the fill-out structural description into a physical layout. A number of algorithm-specific ICs designed with Lager have been fabricated and tested. A robot-control chip is described.<>
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