Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47170
Y. Tamir, T. Frazier
An application-transparent, process-level, distributed error recovery scheme for multicomputers is proposed. Checkpointing is initiated by timers at intervals determined by the needs of the application. Checkpointing and recovery involve only as much of the system as is necessary: a set of interacting processes. Processes that are not part of the interacting set do not participate in checkpointing or recovery and continue to do useful work. Several checkpoint and/or recovery session may be active simultaneously. The scheme does not require significant overhead during normal operation, since it is not necessary to make message transmission atomic, acknowledge each message, or transmit checkbits with each packet. Variations of the technique using packet-switching or virtual circuits are discussed, and the scheme is compared to previously published techniques.<>
{"title":"Application-transparent process-level error recovery for multicomputers","authors":"Y. Tamir, T. Frazier","doi":"10.1109/HICSS.1989.47170","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47170","url":null,"abstract":"An application-transparent, process-level, distributed error recovery scheme for multicomputers is proposed. Checkpointing is initiated by timers at intervals determined by the needs of the application. Checkpointing and recovery involve only as much of the system as is necessary: a set of interacting processes. Processes that are not part of the interacting set do not participate in checkpointing or recovery and continue to do useful work. Several checkpoint and/or recovery session may be active simultaneously. The scheme does not require significant overhead during normal operation, since it is not necessary to make message transmission atomic, acknowledge each message, or transmit checkbits with each packet. Variations of the technique using packet-switching or virtual circuits are discussed, and the scheme is compared to previously published techniques.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124185123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47141
N. Vidovic, D. Siewiorek, D. Vrsalovic, Z. Segall
A description is given of the issues encountered in generating an integrated design environment (IDE) based on the DEMETER workbench (DWB) and PIE (a parallel programming and instrumentation environment for UNIX machines). Some of the reasons for using a general integration methodology are explained. DEMETER, which supports complexity reduction, CAD tools management and manipulation, and distributed/parallel problem-solving, is presented. DWB is described. It is shown how the IDE can be built using the DWB and the basic concepts developed in PIE.<>
{"title":"Towards a consistent view of the design tools and process in distributed problem solving environment","authors":"N. Vidovic, D. Siewiorek, D. Vrsalovic, Z. Segall","doi":"10.1109/HICSS.1989.47141","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47141","url":null,"abstract":"A description is given of the issues encountered in generating an integrated design environment (IDE) based on the DEMETER workbench (DWB) and PIE (a parallel programming and instrumentation environment for UNIX machines). Some of the reasons for using a general integration methodology are explained. DEMETER, which supports complexity reduction, CAD tools management and manipulation, and distributed/parallel problem-solving, is presented. DWB is described. It is shown how the IDE can be built using the DWB and the basic concepts developed in PIE.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120891053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47142
J. Pendleton, C. Burns
An integrated CAD (computer-aided design) environment that leverages publicly available CAD tools is described. Tools not suitably available and tools integration software are added to this base set of tools to complete the system. The CAD system is based on a top-down design and verification methodology that includes feedback from lower design levels to higher levels. At its heart are central data structures containing all design and characterization information. Software layers built on the central data structures include object manipulators to access the data structures; readers and writers for format conversion; CAD tools for synthesis, simulation, comparison, back annotation, and translation; and shell scripts performing tasks of the methodology. Design entry can be done with both schematics and algorithmic description. Both entry forms update the central data structures, thus ensuring consistency of all design descriptions.<>
{"title":"An integrated CAD environment for system design","authors":"J. Pendleton, C. Burns","doi":"10.1109/HICSS.1989.47142","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47142","url":null,"abstract":"An integrated CAD (computer-aided design) environment that leverages publicly available CAD tools is described. Tools not suitably available and tools integration software are added to this base set of tools to complete the system. The CAD system is based on a top-down design and verification methodology that includes feedback from lower design levels to higher levels. At its heart are central data structures containing all design and characterization information. Software layers built on the central data structures include object manipulators to access the data structures; readers and writers for format conversion; CAD tools for synthesis, simulation, comparison, back annotation, and translation; and shell scripts performing tasks of the methodology. Design entry can be done with both schematics and algorithmic description. Both entry forms update the central data structures, thus ensuring consistency of all design descriptions.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127401334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47144
G. Hachtel, M. Lightner, K. Bartlett, D. Bostwick, R. Jacoby, P. Moceyunas, C. Morrison, X. Du, E. Schwarz
The BOLD (Boulder-Optimal Logic Design) system is a set of software tools that optimally transform an arbitrary combinational logic description into a standard cell, gate array, or complex CMOS gate technology. The design philosophy and structure of BOLD are summarized, and the various software tools and algorithms that comprise the BOLD system are described. The input to BOLD is either a behavioral circuit description or a Logical Interchange Format (LIF) file. The output is a netlist consisting of gates from a user supplied library or a netlist of CMOS complex gates. The philosophy of BOLD is contrasted with that of other available synthesis programs (most notably MIS and YLE), and the output of each is compared on a small set of examples.<>
{"title":"BOLD: The Boulder Optimal Logic Design system","authors":"G. Hachtel, M. Lightner, K. Bartlett, D. Bostwick, R. Jacoby, P. Moceyunas, C. Morrison, X. Du, E. Schwarz","doi":"10.1109/HICSS.1989.47144","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47144","url":null,"abstract":"The BOLD (Boulder-Optimal Logic Design) system is a set of software tools that optimally transform an arbitrary combinational logic description into a standard cell, gate array, or complex CMOS gate technology. The design philosophy and structure of BOLD are summarized, and the various software tools and algorithms that comprise the BOLD system are described. The input to BOLD is either a behavioral circuit description or a Logical Interchange Format (LIF) file. The output is a netlist consisting of gates from a user supplied library or a netlist of CMOS complex gates. The philosophy of BOLD is contrasted with that of other available synthesis programs (most notably MIS and YLE), and the output of each is compared on a small set of examples.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116988271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47152
L. Carr, R. Kibler, S. Hippen, T. Gargrave
A 3-D computer is characterized by sufficient speed of CPU computation, high I/O throughput, and an efficient interrupt-handling capability. The architecture of a high-performance 32-bit three-dimensional (3-D) computer, based on a custom-designed VSLI chip set is described. The G-32 consists of a single-board CPU, up to two single-board dual-bus input/output sequencers, and a memory subsystem expandable from 2 to 256 Mbytes. Up to four CPUs and four sequencers can be configured together in a multiprocessor system. The G-32 system is intended for use in real-time, time-sharing processing applications. It uses advanced high-performance CMOS gate arrays and standard cell devices. Floating-point operations have been improved with the addition of a hardware accelerator.<>
{"title":"G-32-a high performance VSLI 3-D computer","authors":"L. Carr, R. Kibler, S. Hippen, T. Gargrave","doi":"10.1109/HICSS.1989.47152","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47152","url":null,"abstract":"A 3-D computer is characterized by sufficient speed of CPU computation, high I/O throughput, and an efficient interrupt-handling capability. The architecture of a high-performance 32-bit three-dimensional (3-D) computer, based on a custom-designed VSLI chip set is described. The G-32 consists of a single-board CPU, up to two single-board dual-bus input/output sequencers, and a memory subsystem expandable from 2 to 256 Mbytes. Up to four CPUs and four sequencers can be configured together in a multiprocessor system. The G-32 system is intended for use in real-time, time-sharing processing applications. It uses advanced high-performance CMOS gate arrays and standard cell devices. Floating-point operations have been improved with the addition of a hardware accelerator.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124964686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47155
S. Bavuso, P. Miner
Research that is being conducted to characterize the latent fault in digital fault-tolerant systems is addressed. A series of investigations that have led to the development of a practical high-speed gate-level logic simulator is described. The validation of the high-speed simulator, using faultable software, and hardware simulations of a prototype MIS-STD-1750A processor are discussed.<>
{"title":"Characterization of the faulted behavior of digital computers and fault tolerant systems","authors":"S. Bavuso, P. Miner","doi":"10.1109/HICSS.1989.47155","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47155","url":null,"abstract":"Research that is being conducted to characterize the latent fault in digital fault-tolerant systems is addressed. A series of investigations that have led to the development of a practical high-speed gate-level logic simulator is described. The validation of the high-speed simulator, using faultable software, and hardware simulations of a prototype MIS-STD-1750A processor are discussed.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128391443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47177
D. McBurney, M. Sleep
A number of experiments with a virtual process tree architecture called ZAPP (zero assignment parallel processor) are described. These experiments were performed using a network of Inmos transputers. Most of the experiments involve the parallel execution of simple process trees grown by rewrite rules that recursively decompose a large grain of work into smaller grains. Some experiments extend the model by supporting limited notions of global communication in the process tree. The basic principles of the ZAPP architecture are presented, and implementation details of a ZAPP kernel used to perform the experiments on a network of Inmos transputers are given. Results of early parallel experiments covering specific applications are described and compared with direct sequential execution on a single transputer. The results confirm earlier sequential simulation experiments, which showed that nearly 100% processor utilization can be obtained for problems that generate process trees much larger than the physical architecture. They also show that real speedups can be obtained with relatively low degrees of parallelism.<>
{"title":"Experiments with a virtual tree machine using transputers","authors":"D. McBurney, M. Sleep","doi":"10.1109/HICSS.1989.47177","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47177","url":null,"abstract":"A number of experiments with a virtual process tree architecture called ZAPP (zero assignment parallel processor) are described. These experiments were performed using a network of Inmos transputers. Most of the experiments involve the parallel execution of simple process trees grown by rewrite rules that recursively decompose a large grain of work into smaller grains. Some experiments extend the model by supporting limited notions of global communication in the process tree. The basic principles of the ZAPP architecture are presented, and implementation details of a ZAPP kernel used to perform the experiments on a network of Inmos transputers are given. Results of early parallel experiments covering specific applications are described and compared with direct sequential execution on a single transputer. The results confirm earlier sequential simulation experiments, which showed that nearly 100% processor utilization can be obtained for problems that generate process trees much larger than the physical architecture. They also show that real speedups can be obtained with relatively low degrees of parallelism.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126288997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47137
M. Andrews
A novel hardware prototyper is described for rapid retargeting of hardware and compilers. Architects can directly create a machine organization, using compiler support design tradeoffs. This rapid prototyping tool features relatively simple hosting (on a PC-AT), diverse target architectures, and minimal use of host memory. It provides simple and rapid retargeting through careful utilization of code transformations and expansions internal to the tool. It can be used to test computing hardware by the direct simulation of applications code written in C. Optimization techniques are applied both at the language-dependent level to the intermediate form by shape analysis and during code generation through cost analysis. A major advantage is a significant reduction in microcode development time.<>
{"title":"Rapid architecture prototyper (RAP)","authors":"M. Andrews","doi":"10.1109/HICSS.1989.47137","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47137","url":null,"abstract":"A novel hardware prototyper is described for rapid retargeting of hardware and compilers. Architects can directly create a machine organization, using compiler support design tradeoffs. This rapid prototyping tool features relatively simple hosting (on a PC-AT), diverse target architectures, and minimal use of host memory. It provides simple and rapid retargeting through careful utilization of code transformations and expansions internal to the tool. It can be used to test computing hardware by the direct simulation of applications code written in C. Optimization techniques are applied both at the language-dependent level to the intermediate form by shape analysis and during code generation through cost analysis. A major advantage is a significant reduction in microcode development time.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122404904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47159
D. Velasevic, M. Bojovic
A novel approach is presented to the hardware implementation of the operations of relational algebra. A sorting algorithm that is suitable for hardware implementation is proposed. It can be applied to conventional computer systems without changing their architecture. For its implementation a sorting circuit is proposed whose processing time is linearly proportional to the number of data sorted. The use of the sorting scheme as a basis for exceptionally efficient hardware support to the operations of relational algebra, such as intersection, difference, join, and natural join, is discussed.<>
{"title":"Hardware support to operations of relational algebra","authors":"D. Velasevic, M. Bojovic","doi":"10.1109/HICSS.1989.47159","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47159","url":null,"abstract":"A novel approach is presented to the hardware implementation of the operations of relational algebra. A sorting algorithm that is suitable for hardware implementation is proposed. It can be applied to conventional computer systems without changing their architecture. For its implementation a sorting circuit is proposed whose processing time is linearly proportional to the number of data sorted. The use of the sorting scheme as a basis for exceptionally efficient hardware support to the operations of relational algebra, such as intersection, difference, join, and natural join, is discussed.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122589935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47178
D. Nicole
The author describes concurrent-processing computers capable of performance in the gigaflop (billions of floating-point operators) range on real scientific and engineering applications, which have ben developed as part of Esprit project 805. The architecture is readily scalable up to over a thousand processors and provides genuinely cost-effective computing on a worthwhile range of problems. Real-time applications are also supported, using optional high-bandwidth input-output facilities.<>
{"title":"Reconfigurable transputer processor architectures","authors":"D. Nicole","doi":"10.1109/HICSS.1989.47178","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47178","url":null,"abstract":"The author describes concurrent-processing computers capable of performance in the gigaflop (billions of floating-point operators) range on real scientific and engineering applications, which have ben developed as part of Esprit project 805. The architecture is readily scalable up to over a thousand processors and provides genuinely cost-effective computing on a worthwhile range of problems. Real-time applications are also supported, using optional high-bandwidth input-output facilities.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131184476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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