Border Trap Based Modeling of SiC Transistor Transfer Characteristics

Abstract

We experimentally and theoretically study the impact of interface and border traps on the transfer characteristics of 4H-SiC transistors measured over a wide temperature range of 200-350 K. Quite apparently, the experimental current-voltage characteristics have drain currents which are much lower than those obtained from simulations performed without traps. Moreover, currents increase with temperature over the entire gate voltage range, while the threshold voltage shifts towards lower values as temperature increases. We show that although interface traps can explain ${I}_{{\mathrm {d}}}-{V}_{{\mathrm {gs}}}$ curves measured at room temperature with good accuracy it fails for lower temperatures. Inclusion of border traps, on the other hand, results in good agreement between experimental and simulated current-voltage characteristics over the entire temperature range. For the first time we were able to successfully represent transfer characteristics of a 4H-SiC transistor at temperatures substantially below 300 K. Therefore, we conclude that border traps are responsible for the complicated behavior of $\mathrm{I}_{{\mathrm {d}}}-\mathrm{V}_{{\mathrm {gs}}}$ characteristics.