Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing

Abstract

Implementation of shortest path algorithm in FPGA has been recently proposed for solving the network routing problem. This paper discusses the architecture and implementation of shortest path algorithms for Floyd-Warshall algorithm and the parallel implementation of Bellman-Ford algorithm in the Binary Relation Inference Network architecture. There are significant differences in the performance of computing shortest paths for these two different approaches. The computation speed and resource consumption issues are discussed. An alternative, serial implementation of the synchronized inference network for single-destination problem is also explored, with emphasis on computation time, resource consumption, and scaling problem size.