Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188691
S. V. Gheorghita, W. Wong, T. Mitra, S. Talla
Reconfigurable computing offers the embedded systems designers the flexibility of application specific optimizations on a generic platform. In this paper, we are concerned with a fine-grain, tightly coupled, dynamically reconfigurable architecture we call Adaptive EPIC. A generic EPIC architecture is augmented with a dynamically reconfigurable structure. In this paper, we describe an experimental setup to evaluate the performance of such a processor. Our results show that such architecture can offer significant performance improvements for low frequency, and hence low power, core processors.
{"title":"A co-simulation study of adaptive EPIC computing","authors":"S. V. Gheorghita, W. Wong, T. Mitra, S. Talla","doi":"10.1109/FPT.2002.1188691","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188691","url":null,"abstract":"Reconfigurable computing offers the embedded systems designers the flexibility of application specific optimizations on a generic platform. In this paper, we are concerned with a fine-grain, tightly coupled, dynamically reconfigurable architecture we call Adaptive EPIC. A generic EPIC architecture is augmented with a dynamically reconfigurable structure. In this paper, we describe an experimental setup to evaluate the performance of such a processor. Our results show that such architecture can offer significant performance improvements for low frequency, and hence low power, core processors.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114681527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188728
A. Carreira, T. W. Fox, L. Turner
A simulated annealing design method for low hardware cost bit-serial Lossless Discrete Integrator (LDI) recursive digital filter implementations using Field Programmable Gate Arrays (FPGAs) with JBits/spl trade/ is presented. This method jointly minimizes the magnitude frequency response error and the filter hardware cost. The next-neighbor connectivity of bit-serial systems is exploited to create a placement method using JBits/spl trade/ to avoid time-consuming general-purpose placement tools for FPGAs in addition to the hardware cost reduction benefits of bit-serial architectures. A design example using the proposed method is presented in which a 30.2 percent hardware cost reduction is obtained.
{"title":"A method of implementing bit-serial LDI ladder filters in FPGAs using JBits","authors":"A. Carreira, T. W. Fox, L. Turner","doi":"10.1109/FPT.2002.1188728","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188728","url":null,"abstract":"A simulated annealing design method for low hardware cost bit-serial Lossless Discrete Integrator (LDI) recursive digital filter implementations using Field Programmable Gate Arrays (FPGAs) with JBits/spl trade/ is presented. This method jointly minimizes the magnitude frequency response error and the filter hardware cost. The next-neighbor connectivity of bit-serial systems is exploited to create a placement method using JBits/spl trade/ to avoid time-consuming general-purpose placement tools for FPGAs in addition to the hardware cost reduction benefits of bit-serial architectures. A design example using the proposed method is presented in which a 30.2 percent hardware cost reduction is obtained.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117114786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188716
S. Komatsu, Yoshihisa Kojima, H. Saito, Kenshu Seto, M. Fujita
In the age of highly integrated system LSIs, the problem of design methodologies with short time-to-market and higher re-programmability after the chip fabrications has acquired great importance. Although a pure FPGA system is one of the solutions, it cannot give sufficient performance in many real-time applications due to its lower performance and higher power dissipation compared to ASICs. Instead, a hardware/software co-design approach can give best design solutions in terms of such design criteria. In this paper, we introduce a new VLSI architecture called Field Modifiable Architecture (FMA) and its design methodology. Experimental results confirm that our architecture can achieve significant performance improvement in terms of execution cycles.
{"title":"Field modifiable architecture with FPGAs and its design methodology","authors":"S. Komatsu, Yoshihisa Kojima, H. Saito, Kenshu Seto, M. Fujita","doi":"10.1109/FPT.2002.1188716","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188716","url":null,"abstract":"In the age of highly integrated system LSIs, the problem of design methodologies with short time-to-market and higher re-programmability after the chip fabrications has acquired great importance. Although a pure FPGA system is one of the solutions, it cannot give sufficient performance in many real-time applications due to its lower performance and higher power dissipation compared to ASICs. Instead, a hardware/software co-design approach can give best design solutions in terms of such design criteria. In this paper, we introduce a new VLSI architecture called Field Modifiable Architecture (FMA) and its design methodology. Experimental results confirm that our architecture can achieve significant performance improvement in terms of execution cycles.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127135182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188657
T. Makimoto
A historical review of the chip industry will be provided with the emphasis on the cyclical nature between standardization direction and customization direction. The basic mechanisms of the cycle will be discussed including technology factors and marketing factors. It is concluded that the field programmable technology will play the vital role in the emerging digital consumer market by providing features that are "standardized in manufacturing but customized in application".
{"title":"The hot decade of field programmable technologies","authors":"T. Makimoto","doi":"10.1109/FPT.2002.1188657","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188657","url":null,"abstract":"A historical review of the chip industry will be provided with the emphasis on the cyclical nature between standardization direction and customization direction. The basic mechanisms of the cycle will be discussed including technology factors and marketing factors. It is concluded that the field programmable technology will play the vital role in the emerging digital consumer market by providing features that are \"standardized in manufacturing but customized in application\".","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127231052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188726
C. Hinkelbein, R. Männer
This work extends RHCS with the capability to link to additional libraries at runtime just by specifying the libraries' filenames. The software components defined in the libraries are made available to the system by means of prototypes. By retaining the abstract interfaces from RHCS we are now able to dynamically compose a complete control framework at runtime without referring to any implementation of the components as building blocks. Also it is possible to extend and adapt the software at runtime according to the needs of reconfigured hardware, or even switch to emulation mode without recompiling the software. Additional components can be build and loaded independently of the existing runtime. This leads to the possibility to build the control software from a textual database describing the hardwares properties. Another possibility would be to use a graphical editor to compose the components to a running system. The performance overhead due to software indirection is monitored and the correctness of architecture is verified by implementing a functional prototype.
{"title":"Reconfigurable hardware control software using anonymous libraries","authors":"C. Hinkelbein, R. Männer","doi":"10.1109/FPT.2002.1188726","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188726","url":null,"abstract":"This work extends RHCS with the capability to link to additional libraries at runtime just by specifying the libraries' filenames. The software components defined in the libraries are made available to the system by means of prototypes. By retaining the abstract interfaces from RHCS we are now able to dynamically compose a complete control framework at runtime without referring to any implementation of the components as building blocks. Also it is possible to extend and adapt the software at runtime according to the needs of reconfigured hardware, or even switch to emulation mode without recompiling the software. Additional components can be build and loaded independently of the existing runtime. This leads to the possibility to build the control software from a textual database describing the hardwares properties. Another possibility would be to use a graphical editor to compose the components to a running system. The performance overhead due to software indirection is monitored and the correctness of architecture is verified by implementing a functional prototype.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125010435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188694
J. L. Núñez, Simon Jones
This paper presents a high-performance application specific architecture for real time lossless data compression, which enables data throughputs over 1.5 Gbits/s compression and decompression using contemporary low-cost re-programmable FPGA technology. The implementation is embedded into a PCI-based system and tested at speed using a PC as the host computer.. A single FPGA is used to map all the functions in the system including the compression and decompressor cores, DMA logic, control logic and Master/Target PCI core. The independent compression and decompression channels enable a combined compression and decompression performance over 3 Gbits/s and robust self-checking hardware where each compress block can be automatically decompressed to defect hardware failures or errors introduced by the communication channel.
{"title":"Lossless data compression programmable hardware for high-speed data networks","authors":"J. L. Núñez, Simon Jones","doi":"10.1109/FPT.2002.1188694","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188694","url":null,"abstract":"This paper presents a high-performance application specific architecture for real time lossless data compression, which enables data throughputs over 1.5 Gbits/s compression and decompression using contemporary low-cost re-programmable FPGA technology. The implementation is embedded into a PCI-based system and tested at speed using a PC as the host computer.. A single FPGA is used to map all the functions in the system including the compression and decompressor cores, DMA logic, control logic and Master/Target PCI core. The independent compression and decompression channels enable a combined compression and decompression performance over 3 Gbits/s and robust self-checking hardware where each compress block can be automatically decompressed to defect hardware failures or errors introduced by the communication channel.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115516923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188713
C. Rambabu, L. Chakrabarti, Anil Mahanta
This paper proposes a fast watershed algorithm derived from Meyer's simulated flooding based algorithm. The parallel processing adopted in conditional neighborhood comparisons for processing 3/spl times/3 pixels in one process leads to reduced computational complexity compared to Meyer's algorithm. The proposed algorithm has been implemented in an Xilinx FPGA environment.
{"title":"An efficient architecture for an improved watershed algorithm and its FPGA implementation","authors":"C. Rambabu, L. Chakrabarti, Anil Mahanta","doi":"10.1109/FPT.2002.1188713","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188713","url":null,"abstract":"This paper proposes a fast watershed algorithm derived from Meyer's simulated flooding based algorithm. The parallel processing adopted in conditional neighborhood comparisons for processing 3/spl times/3 pixels in one process leads to reduced computational complexity compared to Meyer's algorithm. The proposed algorithm has been implemented in an Xilinx FPGA environment.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131530695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188696
S. Jain, Anshul Kumar, Shashi Kumar
In rapid prototyping system application, any large digital circuit can be implemented onto Multi-FPGA Board(MFB). Key MFB architectural feature is its inter-FPGA connections consisting of fixed connections(FC) i.e. FPGA-FPGA connections and programmable connections(PC) i.e. FPGA-programmable switch like FPID-FPGA. MFBs consisting of both the types of connections are known as hybrid MFBs. Since, PC requires two wires as against one wire in FC, MFB must have minimum number of PCs to keep fabrication easy. In partitioned circuit, multi-terminal nets (MTNs) are distributed over one or more circuit parts. When each circuit part is implemented over one FPGA, the MTNs between circuit parts will be routed over PCs and FCs between corresponding FPGAs. Multi-hop routers are used to minimize the use of PCs, but they increase source to sink delay with increasing number of hops. A generic multi-hop router to route two-terminal nets, which obeys the given limit on hops, was presented in our previous work [2002]. In this paper, we extend the same to route multi-terminal nets.
{"title":"Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards","authors":"S. Jain, Anshul Kumar, Shashi Kumar","doi":"10.1109/FPT.2002.1188696","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188696","url":null,"abstract":"In rapid prototyping system application, any large digital circuit can be implemented onto Multi-FPGA Board(MFB). Key MFB architectural feature is its inter-FPGA connections consisting of fixed connections(FC) i.e. FPGA-FPGA connections and programmable connections(PC) i.e. FPGA-programmable switch like FPID-FPGA. MFBs consisting of both the types of connections are known as hybrid MFBs. Since, PC requires two wires as against one wire in FC, MFB must have minimum number of PCs to keep fabrication easy. In partitioned circuit, multi-terminal nets (MTNs) are distributed over one or more circuit parts. When each circuit part is implemented over one FPGA, the MTNs between circuit parts will be routed over PCs and FCs between corresponding FPGAs. Multi-hop routers are used to minimize the use of PCs, but they increase source to sink delay with increasing number of hops. A generic multi-hop router to route two-terminal nets, which obeys the given limit on hops, was presented in our previous work [2002]. In this paper, we extend the same to route multi-terminal nets.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128289562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188722
Jun Jiang, W. Luk, D. Rueckert
This paper describes techniques for producing FPGA-based designs that support free-form deformation in medical image processing. The free-form deformation method is based on a B-spline algorithm for modelling three-dimensional deformable objects. Our design includes four optimisations. First, we store the values of a third-order B-spline model in lookup tables. Second, we adopt a customised number representation format in our implementation. Third, we transform a nested loop so that conditionals are moved outside the loop. Fourth, we pipeline the design to increase its throughput, and we also deploy multiple pipelines such that each covers a different image. Our design description, captured in the Handel-C language, is parameterisable at compile time to support a range of image resolutions and computational precisions. An implementation on a Xilinx XC2V6000 device would be capable of processing images of resolution up to 256 by 256 pixels in real time.
{"title":"FPGA-based computation of free-form deformations","authors":"Jun Jiang, W. Luk, D. Rueckert","doi":"10.1109/FPT.2002.1188722","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188722","url":null,"abstract":"This paper describes techniques for producing FPGA-based designs that support free-form deformation in medical image processing. The free-form deformation method is based on a B-spline algorithm for modelling three-dimensional deformable objects. Our design includes four optimisations. First, we store the values of a third-order B-spline model in lookup tables. Second, we adopt a customised number representation format in our implementation. Third, we transform a nested loop so that conditionals are moved outside the loop. Fourth, we pipeline the design to increase its throughput, and we also deploy multiple pipelines such that each covers a different image. Our design description, captured in the Handel-C language, is parameterisable at compile time to support a range of image resolutions and computational precisions. An implementation on a Xilinx XC2V6000 device would be capable of processing images of resolution up to 256 by 256 pixels in real time.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125316483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188688
Eric Roesler, B. Nelson
The combining of one or more CPU's and an FPGA fabric on the same die is growing in popularity. Such programmable system-on-chip (PSOC) systems promise performance and development time advantages over conventional technology. In a PSOC design, design errors may occur in many different places - the design of the CPU, the embedded software, the FPGA-based parts of the design, or the interfaces between these various parts. This paper presents a flexible tool that allows the user to dynamically adapt the CAD tool's behavior to the level of detail needed to track down design errors in PSOC designs. It provides for the creation of and coexistence of software source debuggers and gate level debug tools, all incorporated into the same debugging environment. A prototype PSOC debugging system based on a derivative of the JHDL CAD tool is presented which illustrates the range of debug support in both simulation and hardware execution modes that can be provided for PSOC debug. Extensions to the tool to support a wider range of embedded processors and GNU compiler tools are discussed along with conclusions and future work.
{"title":"Debug methods for hybrid CPU/FPGA systems","authors":"Eric Roesler, B. Nelson","doi":"10.1109/FPT.2002.1188688","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188688","url":null,"abstract":"The combining of one or more CPU's and an FPGA fabric on the same die is growing in popularity. Such programmable system-on-chip (PSOC) systems promise performance and development time advantages over conventional technology. In a PSOC design, design errors may occur in many different places - the design of the CPU, the embedded software, the FPGA-based parts of the design, or the interfaces between these various parts. This paper presents a flexible tool that allows the user to dynamically adapt the CAD tool's behavior to the level of detail needed to track down design errors in PSOC designs. It provides for the creation of and coexistence of software source debuggers and gate level debug tools, all incorporated into the same debugging environment. A prototype PSOC debugging system based on a derivative of the JHDL CAD tool is presented which illustrates the range of debug support in both simulation and hardware execution modes that can be provided for PSOC debug. Extensions to the tool to support a wider range of embedded processors and GNU compiler tools are discussed along with conclusions and future work.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126088750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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