K. Itoh, R. Hori, Jun Etoh, S. Asai, N. Hashimoto, K. Yagi, H. Sunami
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引用次数: 63
Abstract
This paper will report on an experimental 21μm2cell, single 5V 1Mb NMOS DRAM. Typical clata are: access time 90ns, power dissipation 300mW at 260ns cycle time. Chip area is 46mm2
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