Pub Date : 1984-02-01DOI: 10.1109/ISSCC.1984.1156579
Y. Kuraishi, K. Nakayama, K. Miyadera
A speech spectrum analyzer, including a 20-channel filter bank and a 9b resolution ADC will be described. By using multiplexed switched capacitor filters, a chip area of 23mm2and power consumption of 74mW have been acheived.
{"title":"A single-chip 20 channel speech spectrum analyzer","authors":"Y. Kuraishi, K. Nakayama, K. Miyadera","doi":"10.1109/ISSCC.1984.1156579","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156579","url":null,"abstract":"A speech spectrum analyzer, including a 20-channel filter bank and a 9b resolution ADC will be described. By using multiplexed switched capacitor filters, a chip area of 23mm2and power consumption of 74mW have been acheived.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXVII 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129853841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156584
A. Abidi, B. Kasper, R. Kushner
Two broadband transresistance amplifiers with bandwidths of about 700MHz, using one micron channel length NMOS devices, and incorporating a voltage controllable gain stage and a temperature tracking circuit, will be reported. One amplifier has been used as a front end for a fiber optics system operating at 800Mb/s.
{"title":"Fine line NMOS transresistance amplifiers","authors":"A. Abidi, B. Kasper, R. Kushner","doi":"10.1109/ISSCC.1984.1156584","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156584","url":null,"abstract":"Two broadband transresistance amplifiers with bandwidths of about 700MHz, using one micron channel length NMOS devices, and incorporating a voltage controllable gain stage and a temperature tracking circuit, will be reported. One amplifier has been used as a front end for a fiber optics system operating at 800Mb/s.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123057417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156592
S. Suzuki, M. Nakao, T. Takeshima, M. Yoshida, M. Kikuchi, K. Nakamura
THE DESIGN OF A 128K word x 8b MOS DRAM, which has a 120ns access time and 290mW power dissipation, will be described. In realizing the chip, 1p.m NMOS technology, with double level aluminum construction, has been utilized. The chip is non-address-multiplexed and accomodated in a 30-pin package; Figure 1. The RAM has operated on all memory cells. One of the major purposes of the project to be reported was to establish and demonstrate low-noise circuit technology. A dummy reversal technique, was adopted to introduce the half Vcc bit line precharge technique with dummy cells. A noise evaluation simulation in cell-array designing, based on a three dimensional capacitance calculation, was also conducted. Extensive utilization of double-level aluminum wiring, not only in the memory cell array, but also in peripheral circuits, has reduced substantially circuit noise. Moreover, it has drastically cut the time required for chip layout, while the cell occupation ratio is over 60%.
{"title":"A 128K word × 8b DRAM","authors":"S. Suzuki, M. Nakao, T. Takeshima, M. Yoshida, M. Kikuchi, K. Nakamura","doi":"10.1109/ISSCC.1984.1156592","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156592","url":null,"abstract":"THE DESIGN OF A 128K word x 8b MOS DRAM, which has a 120ns access time and 290mW power dissipation, will be described. In realizing the chip, 1p.m NMOS technology, with double level aluminum construction, has been utilized. The chip is non-address-multiplexed and accomodated in a 30-pin package; Figure 1. The RAM has operated on all memory cells. One of the major purposes of the project to be reported was to establish and demonstrate low-noise circuit technology. A dummy reversal technique, was adopted to introduce the half Vcc bit line precharge technique with dummy cells. A noise evaluation simulation in cell-array designing, based on a three dimensional capacitance calculation, was also conducted. Extensive utilization of double-level aluminum wiring, not only in the memory cell array, but also in peripheral circuits, has reduced substantially circuit noise. Moreover, it has drastically cut the time required for chip layout, while the cell occupation ratio is over 60%.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123459113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/isscc.1984.1156665
D. Rinerson, M. Ahrens, Jih Lein, B. Venkatesh, Tien Lin, P. Song, S. Longcor, L. Shen, D. Rogers, M. Briner
EPROMs utilizing double polysilicon floating gate technology that achieve bit densities through 64Kb to 512Kb and access times of 150ns will be reported. Through the use of an NMOS process with 1.7μm design rules, a minimum cell size of 36.6μm2has been obtained.
{"title":"512K EPROMs","authors":"D. Rinerson, M. Ahrens, Jih Lein, B. Venkatesh, Tien Lin, P. Song, S. Longcor, L. Shen, D. Rogers, M. Briner","doi":"10.1109/isscc.1984.1156665","DOIUrl":"https://doi.org/10.1109/isscc.1984.1156665","url":null,"abstract":"EPROMs utilizing double polysilicon floating gate technology that achieve bit densities through 64Kb to 512Kb and access times of 150ns will be reported. Through the use of an NMOS process with 1.7μm design rules, a minimum cell size of 36.6μm2has been obtained.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"416 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122862730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156711
M. Isobe, J. Matsunaga, T. Sakurai, T. Ohtani, K. Sawada, H. Nozawa, T. Iizuka, S. Kohyama
A 46ns 32K×8 CMOS RAM fabricated with double metal, double poly 1.2μm P-well technology will be reported. The RAM(59.2mm2) has a 10mW operating power at 1MHz and a 30μW standby power.
{"title":"A 46ns 256K CMOS SRAM","authors":"M. Isobe, J. Matsunaga, T. Sakurai, T. Ohtani, K. Sawada, H. Nozawa, T. Iizuka, S. Kohyama","doi":"10.1109/ISSCC.1984.1156711","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156711","url":null,"abstract":"A 46ns 32K×8 CMOS RAM fabricated with double metal, double poly 1.2μm P-well technology will be reported. The RAM(59.2mm<sup>2</sup>) has a 10mW operating power at 1MHz and a 30μW standby power.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"61 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116812373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156685
C. Schmitz, H. Hingarh, M. Brown, Hang Kwan, J. Vithayathil
This paper will cover a 4ns compatible ECL field programmable logic array, organized16×24×(8+bar{8})with true and complement output. Features include vertical junction fuses as programmable elements and built-in test.
{"title":"An ECL field programmable logic array","authors":"C. Schmitz, H. Hingarh, M. Brown, Hang Kwan, J. Vithayathil","doi":"10.1109/ISSCC.1984.1156685","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156685","url":null,"abstract":"This paper will cover a 4ns compatible ECL field programmable logic array, organized16×24×(8+bar{8})with true and complement output. Features include vertical junction fuses as programmable elements and built-in test.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124004982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156597
Jun Iwamura, K. Suganuma, M. Kimura, S. Taguchi
A CMOS/SOS 16b x 16b parallel multiplier with a chip using a modified array to speed arithmetic, performing a 16b x 16b multiplication typically in 27ns, while dissipating 150mW power, will be reported. Functions and pin configuration of the chip have been designed to have upward compatibility with commercially available LSI multipliers*. Figure la shows a fraction of the multiplier array which uses a modified array technique’ in contrast to a conventional carry save adder shown in b . The array consists of odd rows and even rows. Sum and carry signals generated by an odd row are pansferred to the next odd row, and those of an even row are concurrently transferred to the next even row. Therefore, two pairs of sum and carry signal streams are prepared in the array in parallel. In the following stage, the sum of odd rows and of the even rows are added together to produce a final product. Since this modified array has reduced. the number of addition stages by about one half compared to the conventional carry save adder method, the maximum number of adder stages in a column required to accomplish any mode of 16b x 16b multiplication is only nine.
本文将介绍一种CMOS/SOS 16b x 16b并行乘法器，该乘法器采用改进的阵列来加速运算，通常在27ns内执行16b x 16b乘法，而功耗为150mW。芯片的功能和引脚配置已被设计为具有向上兼容商用LSI乘法器*。图a显示了乘法器数组的一小部分，它使用了一种改进的数组技术，与b中所示的传统进位保存加法器形成对比。这个数组由奇数行和偶数行组成。奇数行产生的和、进位信号传输到下一个奇数行，偶数行产生的和、进位信号并发传输到下一个偶数行。因此，在阵列中并行准备了两对和进位信号流。在接下来的阶段，奇数行和偶数行的总和被加在一起产生一个最终产品。因为这个修改过的数组已经减少了。与传统的进位保存加法相比较，加法阶段的数量减少了大约一半，完成任何16b × 16b乘法模式所需的列中的最大加法级数仅为9。
{"title":"A CMOS/SOS multiplier","authors":"Jun Iwamura, K. Suganuma, M. Kimura, S. Taguchi","doi":"10.1109/ISSCC.1984.1156597","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156597","url":null,"abstract":"A CMOS/SOS 16b x 16b parallel multiplier with a chip using a modified array to speed arithmetic, performing a 16b x 16b multiplication typically in 27ns, while dissipating 150mW power, will be reported. Functions and pin configuration of the chip have been designed to have upward compatibility with commercially available LSI multipliers*. Figure la shows a fraction of the multiplier array which uses a modified array technique’ in contrast to a conventional carry save adder shown in b . The array consists of odd rows and even rows. Sum and carry signals generated by an odd row are pansferred to the next odd row, and those of an even row are concurrently transferred to the next even row. Therefore, two pairs of sum and carry signal streams are prepared in the array in parallel. In the following stage, the sum of odd rows and of the even rows are added together to produce a final product. Since this modified array has reduced. the number of addition stages by about one half compared to the conventional carry save adder method, the maximum number of adder stages in a column required to accomplish any mode of 16b x 16b multiplication is only nine.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121194961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156587
D. Dawson, M. Salib, L. Dickens
The modeling and fabrication of a cascode 2-6GHz distributed amplifier with a 1.2:1 input and output VSWR and 4.2dB noise figure will be discussed. The technique for modeling the noise figure extends to an arbitrary combination of active devices in a nodal network.
{"title":"Distributed cascode amplifier and noise figure modeling of an arbitrary amplifier configuration","authors":"D. Dawson, M. Salib, L. Dickens","doi":"10.1109/ISSCC.1984.1156587","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156587","url":null,"abstract":"The modeling and fabrication of a cascode 2-6GHz distributed amplifier with a 1.2:1 input and output VSWR and 4.2dB noise figure will be discussed. The technique for modeling the noise figure extends to an arbitrary combination of active devices in a nodal network.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125205212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156646
S. Sacarisen, M. Stambaugh, P. Lou, A. Khosrovi, Ki Chang
A 16b processor for control of digital communication networks, with 2186 bytes of RAM will be discussed. The chip features include instruction fault detection, I/O parity check/ generation and special test modes.
{"title":"A VLSI communication processor designed for testability","authors":"S. Sacarisen, M. Stambaugh, P. Lou, A. Khosrovi, Ki Chang","doi":"10.1109/ISSCC.1984.1156646","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156646","url":null,"abstract":"A 16b processor for control of digital communication networks, with 2186 bytes of RAM will be discussed. The chip features include instruction fault detection, I/O parity check/ generation and special test modes.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131147145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156604
M. Sato, S. Ogasawara, K. Suzuki
in Figure 2. The delay time difference between two CCD registers (684.5b and 2b) produces a 6 3 . 5 ~ delay time. The IC, using the 684.5b/Zb CCD registers independently can serve as two switchable delay lines, or as two registers together to form a comb filter. The amplitude required for the input clock signal is only lOOmV p-p. Up to 1 V p-p video signals can pass through the delay line without appreciable distortion. The output circuit (Figure 3) contains a double-stage source follower, followed by double stage of a sample and hold circuit and a CMOS inverter amplifier. I n the CMOS circuit the inverter amplifiers have two configurations and are applied in the output circuit. Consequently, a level shift circuit is not necessary between the two inverters. The CMOS inverter amplifier has a wide dynamic range. A comparison of the CMOS inverter amplifier and a conventional N-channel amplifier, together with their total harmonic distortion, is shown in Figure 4. The gain of the amplifier is determined by the transconductance ratio of N-channel and P-channel MOS FETs. Compared to single N-channel inverters, CMOS inverters are free from back gate bias effects. Thus, it is possible to construct high-gain and high-speed amplifiers with CMOS inverters. Characteristic degradations, due to the sample and hold pulse timing, are suppressed by using two-stage sample and hold circuits. The sampling pulse amplitudes are 9V p-p in the first stage and 5V p-p in the second stage insuring a good output signal dynamic range, and a reduction of the sampling pulse coupling.
{"title":"A CMOS CCD video delay line","authors":"M. Sato, S. Ogasawara, K. Suzuki","doi":"10.1109/ISSCC.1984.1156604","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156604","url":null,"abstract":"in Figure 2. The delay time difference between two CCD registers (684.5b and 2b) produces a 6 3 . 5 ~ delay time. The IC, using the 684.5b/Zb CCD registers independently can serve as two switchable delay lines, or as two registers together to form a comb filter. The amplitude required for the input clock signal is only lOOmV p-p. Up to 1 V p-p video signals can pass through the delay line without appreciable distortion. The output circuit (Figure 3) contains a double-stage source follower, followed by double stage of a sample and hold circuit and a CMOS inverter amplifier. I n the CMOS circuit the inverter amplifiers have two configurations and are applied in the output circuit. Consequently, a level shift circuit is not necessary between the two inverters. The CMOS inverter amplifier has a wide dynamic range. A comparison of the CMOS inverter amplifier and a conventional N-channel amplifier, together with their total harmonic distortion, is shown in Figure 4. The gain of the amplifier is determined by the transconductance ratio of N-channel and P-channel MOS FETs. Compared to single N-channel inverters, CMOS inverters are free from back gate bias effects. Thus, it is possible to construct high-gain and high-speed amplifiers with CMOS inverters. Characteristic degradations, due to the sample and hold pulse timing, are suppressed by using two-stage sample and hold circuits. The sampling pulse amplitudes are 9V p-p in the first stage and 5V p-p in the second stage insuring a good output signal dynamic range, and a reduction of the sampling pulse coupling.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127868007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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