ELsim: a timing simulator for digital CMOS integrated circuits

Abstract

The basic operating principles of ELsim, a timing simulator for digital CMOS circuits, are discussed. ELsim uses the electrical-logic, or ELogic, method where time is solved for rather than voltage and an event-driven, selective trace approach is used which exploits circuit latency to improve simulation speed. Voltage levels at the circuit nodes are descretized, and the size of the voltage steps can be increased to trade accuracy for simulation speed. Results of a comparison of the ELsim simulator performance to that of SPICE for sample CMOS circuits are featured. In general, the delay times and waveforms calculated with ELsim show satisfactorily agreement with those obtained using SPICE.<>