A 2.4 V, 700 /spl mu/W, 0.18 mm/sup 2/ second-order demodulator for high-resolution /spl Sigma//spl Delta/ DACs

Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI:10.1109/CICC.1997.606633

Zhongming Shi, K. Hsu, O. Salminen, P. Wang, J. Vahe, K. Kaltiokallio

引用次数: 0

Abstract

This work presents the design and measurement results of a novel second-order demodulator for high-resolution sigma-delta digital to analog converters. The demodulator combines digital to analog converting and second-order lowpass filtering into a single step, therefore, eliminating conventionally required post analog filter. This approach offers a large reduction both in chip size and power consumption. A 14-bit fully differential second-order demodulator has been designed and implemented in a complete 2.4 V cellular baseband chip by using a double-poly and triple-metal 0.5 /spl mu/m low-power CMOS process. The total active chip area and power consumption of the demodulator are 0.18 mm/sup 2/ and 700 /spl mu/W, respectively.

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2.4 V, 700 /spl mu/W, 0.18 mm/sup / 2/二阶解调器，用于高分辨率/spl Sigma//spl Delta/ dac

本文介绍了一种用于高分辨率σ - δ数模转换器的新型二阶解调器的设计和测量结果。该解调器将数模转换和二阶低通滤波结合到一个单步，因此，消除了传统上需要的后模拟滤波器。这种方法大大减小了芯片尺寸和功耗。采用双聚三金属0.5 /spl mu/m低功耗CMOS工艺，在完整的2.4 V蜂窝基带芯片上设计并实现了一个14位全差分二阶解调器。该解调器的总有效芯片面积和功耗分别为0.18 mm/sup 2/和700 /spl mu/W。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of CICC 97 - Custom Integrated Circuits Conference

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