Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606599
G. Yeap
We present a procedure to optimize controllers of a CPU in a high-level description language (HDL) logic synthesis environment. The procedure is optimized for power and area efficiency of the controller. Applying the procedure on an actual controller of a RISC CPU, we realized up to 30% power as well as 20% area reduction compared to an unoptimized design. The procedure is applicable to any synthesizable HDL with symbolic state variables in its behavioral description.
{"title":"CPU controller optimization in HDL logic synthesis","authors":"G. Yeap","doi":"10.1109/CICC.1997.606599","DOIUrl":"https://doi.org/10.1109/CICC.1997.606599","url":null,"abstract":"We present a procedure to optimize controllers of a CPU in a high-level description language (HDL) logic synthesis environment. The procedure is optimized for power and area efficiency of the controller. Applying the procedure on an actual controller of a RISC CPU, we realized up to 30% power as well as 20% area reduction compared to an unoptimized design. The procedure is applicable to any synthesizable HDL with symbolic state variables in its behavioral description.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115370187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606677
K. Mayaram, D.C. Lee, S. Moinian, D. Rich, J. Roychowdhury
Design of the RF section in a communication IC is often a challenging problem. Although several computer-aided analysis tools are available they are not effectively used because there is a lack of understanding about their features and limitations. This paper attempts to explain the simulator-specific terminology without resorting to mathematical details. The shortcomings of conventional SPICE-like simulators and the analyses required for RF applications are described. Various analysis methods that are currently available for RF simulation are presented and commercial simulators are compared in terms of their functionalities and limitations.
{"title":"Overview of computer-aided analysis tools for RFIC simulation: Algorithms, features, and limitations","authors":"K. Mayaram, D.C. Lee, S. Moinian, D. Rich, J. Roychowdhury","doi":"10.1109/CICC.1997.606677","DOIUrl":"https://doi.org/10.1109/CICC.1997.606677","url":null,"abstract":"Design of the RF section in a communication IC is often a challenging problem. Although several computer-aided analysis tools are available they are not effectively used because there is a lack of understanding about their features and limitations. This paper attempts to explain the simulator-specific terminology without resorting to mathematical details. The shortcomings of conventional SPICE-like simulators and the analyses required for RF applications are described. Various analysis methods that are currently available for RF simulation are presented and commercial simulators are compared in terms of their functionalities and limitations.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116797460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606698
I. Kang, A. Willson
An r=1/2, K=9 Viterbi decoder IC for CDMA transceivers consumes 0.24 mW at a power supply voltage of 1.65 V, a data rate of 14.4 kbps, and a clock speed of 0.9216 MHz. Its core consists of approximately 65 k transistors, occupying 1.9/spl times/3.4 mm/sup 2/ in a 0.8-/spl mu/m triple-layer-metal n-well CMOS technology.
{"title":"A 0.24 mW, 14.4 kbps, r=1/2, K=9 Viterbi decoder","authors":"I. Kang, A. Willson","doi":"10.1109/CICC.1997.606698","DOIUrl":"https://doi.org/10.1109/CICC.1997.606698","url":null,"abstract":"An r=1/2, K=9 Viterbi decoder IC for CDMA transceivers consumes 0.24 mW at a power supply voltage of 1.65 V, a data rate of 14.4 kbps, and a clock speed of 0.9216 MHz. Its core consists of approximately 65 k transistors, occupying 1.9/spl times/3.4 mm/sup 2/ in a 0.8-/spl mu/m triple-layer-metal n-well CMOS technology.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126773117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606664
N. Mizukoshi, R. Fan, H. Suzuki, Y. Tomimitsu, N. Sato, H. Ishida, M. Ichihara, K. Kirino, M. Tawada, H. Nagano, M. Shinohara
A single chip controller for the shared buffer ATM switch with 1.2 Gbps switching capacity has been developed for the first time. Using external standard SRAMs enables low cost implementation of cell buffers, header translation tables and control memories. The chip can support various line interface speeds with standard UTOPIA level 2. High throughput multicast switching capability is achieved by novel buffer control scheme, "re-queuing". The chip also supports multiple service classes standardized by the ATM forum. The performance of the developed chip is also evaluated.
{"title":"A single-chip controller for 1.2 Gbps shared buffer ATM switches","authors":"N. Mizukoshi, R. Fan, H. Suzuki, Y. Tomimitsu, N. Sato, H. Ishida, M. Ichihara, K. Kirino, M. Tawada, H. Nagano, M. Shinohara","doi":"10.1109/CICC.1997.606664","DOIUrl":"https://doi.org/10.1109/CICC.1997.606664","url":null,"abstract":"A single chip controller for the shared buffer ATM switch with 1.2 Gbps switching capacity has been developed for the first time. Using external standard SRAMs enables low cost implementation of cell buffers, header translation tables and control memories. The chip can support various line interface speeds with standard UTOPIA level 2. High throughput multicast switching capability is achieved by novel buffer control scheme, \"re-queuing\". The chip also supports multiple service classes standardized by the ATM forum. The performance of the developed chip is also evaluated.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114462858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606587
Z. Czamul, T. Itakura, N. Dobashi, T. Iida, H. Tanimoto
Two new and general methods of a fully balanced (FB) analog system design, which contribute towards achieving both a great reduction of the design time and a high performance system "implementation" are presented. It is shown that a single-ended system based on any type of op amps (rail-to-rail, constant g/sub m/, etc.), realized in any technology (CMOS, bilpolar, BiCMOS, GaAs), can be easily and effectively converted to its FB counterpart in a very practical way. Using the proposed rules, any FB system implementation with op amps (data converter, modulator, filter, etc.) requires only a single-ended system version design and the drawbacks related to a conventional FB system design are avoided. A final schematic/layout of a FB system can be achieved by pattern modification only of double single-ended system schematics/layouts, which are now available in the ASIC libraries of many companies.
{"title":"On changing the shape of ASIC based fully balanced analog system design","authors":"Z. Czamul, T. Itakura, N. Dobashi, T. Iida, H. Tanimoto","doi":"10.1109/CICC.1997.606587","DOIUrl":"https://doi.org/10.1109/CICC.1997.606587","url":null,"abstract":"Two new and general methods of a fully balanced (FB) analog system design, which contribute towards achieving both a great reduction of the design time and a high performance system \"implementation\" are presented. It is shown that a single-ended system based on any type of op amps (rail-to-rail, constant g/sub m/, etc.), realized in any technology (CMOS, bilpolar, BiCMOS, GaAs), can be easily and effectively converted to its FB counterpart in a very practical way. Using the proposed rules, any FB system implementation with op amps (data converter, modulator, filter, etc.) requires only a single-ended system version design and the drawbacks related to a conventional FB system design are avoided. A final schematic/layout of a FB system can be achieved by pattern modification only of double single-ended system schematics/layouts, which are now available in the ASIC libraries of many companies.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128304194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606665
S. Gogaert, M. Steyaert
In high-speed communication systems with multiple inputs from different origins, all data have to be retimed to the clock of the DSP. This paper describes a data-recovery system which allows a 25% tolerance on the absolute position of the edge. The intelligent sample selector with memory-function retrieves the correct data from the multisampled input, even under the circumstances of wander, clock- and data-jitter and propagation phase-shift. The used approach does not require a PLL nor a DLL, since the straightforward mechanism results in the capture of the transmitted data with only the use of the central clock of the DSP. The retiming is done already at the first level-change and further at each following level-change. The good results are proven with measurements on a realisation with standard cells in a standard 0.7 /spl mu/m CMOS technology.
{"title":"A skew tolerant CMOS level-based ATM data-recovery system without PLL topology","authors":"S. Gogaert, M. Steyaert","doi":"10.1109/CICC.1997.606665","DOIUrl":"https://doi.org/10.1109/CICC.1997.606665","url":null,"abstract":"In high-speed communication systems with multiple inputs from different origins, all data have to be retimed to the clock of the DSP. This paper describes a data-recovery system which allows a 25% tolerance on the absolute position of the edge. The intelligent sample selector with memory-function retrieves the correct data from the multisampled input, even under the circumstances of wander, clock- and data-jitter and propagation phase-shift. The used approach does not require a PLL nor a DLL, since the straightforward mechanism results in the capture of the transmitted data with only the use of the central clock of the DSP. The retiming is done already at the first level-change and further at each following level-change. The good results are proven with measurements on a realisation with standard cells in a standard 0.7 /spl mu/m CMOS technology.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128527155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606598
M. Lee, E. Chavez-Reyes, E. Zorinsky
For a large clock net, skew/delay evaluations were carried out using an accurate distributed parasitic network of 3D multilevel interconnect structures. We identified of 3D multilevel interconnect structures. We identified a reliable parasitic distributed RLC extraction method with the bounded local path 3D numerical simulation by using field solver. With the accurate RLC parasitic interconnect network and input driver for traversal clock delay evaluation, we investigated the impacts of variations in input slew, power supply voltage (V/sub cc/), and driver and load gate sizing on clock delay within the slow ramp region of driver gate as well as in the parasitic interconnect network. Input slew was found to be a dominant factor affecting clock delay sensitivity. This suggests that careful sizing of clock drivers, interconnects, and gate loads is required for minimal traversal clock delay. In addition, we used indirect on-chip electron beam probing to confirm that the simulated clock delays were in reasonable agreement with the measured delays.
{"title":"A reliable traversal clock delay evaluation including input slew effect with 3D parasitic interconnect RLC extraction","authors":"M. Lee, E. Chavez-Reyes, E. Zorinsky","doi":"10.1109/CICC.1997.606598","DOIUrl":"https://doi.org/10.1109/CICC.1997.606598","url":null,"abstract":"For a large clock net, skew/delay evaluations were carried out using an accurate distributed parasitic network of 3D multilevel interconnect structures. We identified of 3D multilevel interconnect structures. We identified a reliable parasitic distributed RLC extraction method with the bounded local path 3D numerical simulation by using field solver. With the accurate RLC parasitic interconnect network and input driver for traversal clock delay evaluation, we investigated the impacts of variations in input slew, power supply voltage (V/sub cc/), and driver and load gate sizing on clock delay within the slow ramp region of driver gate as well as in the parasitic interconnect network. Input slew was found to be a dominant factor affecting clock delay sensitivity. This suggests that careful sizing of clock drivers, interconnects, and gate loads is required for minimal traversal clock delay. In addition, we used indirect on-chip electron beam probing to confirm that the simulated clock delays were in reasonable agreement with the measured delays.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124558440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606578
P.M. Lee, T. Seo, K. Ise, A. Hiraishi, O. Nagashima, S. Yoshida
We have applied hot-carrier circuit-level simulation to entire circuits of a few thousand to over 12 K transistors using a simple but accurate degradation model for reliability verification of actual memory products. Previous published applications were small scale (few tens of transistors or individual circuit blocks) or for experimental purposes. By applying simulation to entire circuits, areas with worst degradation are not missed due to simulating only certain circuit blocks. Varying degradation depending upon actual products make accurate total-circuit simulation a crucial part of the early design process as technology advances into the deep sub-micron high clock rate regime.
{"title":"Application of circuit-level hot-carrier reliability simulation to memory design","authors":"P.M. Lee, T. Seo, K. Ise, A. Hiraishi, O. Nagashima, S. Yoshida","doi":"10.1109/CICC.1997.606578","DOIUrl":"https://doi.org/10.1109/CICC.1997.606578","url":null,"abstract":"We have applied hot-carrier circuit-level simulation to entire circuits of a few thousand to over 12 K transistors using a simple but accurate degradation model for reliability verification of actual memory products. Previous published applications were small scale (few tens of transistors or individual circuit blocks) or for experimental purposes. By applying simulation to entire circuits, areas with worst degradation are not missed due to simulating only certain circuit blocks. Varying degradation depending upon actual products make accurate total-circuit simulation a crucial part of the early design process as technology advances into the deep sub-micron high clock rate regime.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130415507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606583
B. R. Veillette, G. Roberts
A novel method for the measurement of the jitter transfer function of digital phase-locked loops is presented. The signal generation and analysis circuits are entirely digital except for an extra charge-pump. They hence do not require calibration. Contrary to other phase-locked loop digital measurement schemes, a clock frequency larger than the phase-locked loop operating frequency is not necessary. Because the area overhead is small, our scheme is highly amenable to on-chip tuning of analog components for compliance to specifications. This method could also be used to implement built-in self-test for phase-locked loops. Experiments with discrete components show the jitter transfer function measuring method is sound.
{"title":"Self-calibration of digital phase-locked loops","authors":"B. R. Veillette, G. Roberts","doi":"10.1109/CICC.1997.606583","DOIUrl":"https://doi.org/10.1109/CICC.1997.606583","url":null,"abstract":"A novel method for the measurement of the jitter transfer function of digital phase-locked loops is presented. The signal generation and analysis circuits are entirely digital except for an extra charge-pump. They hence do not require calibration. Contrary to other phase-locked loop digital measurement schemes, a clock frequency larger than the phase-locked loop operating frequency is not necessary. Because the area overhead is small, our scheme is highly amenable to on-chip tuning of analog components for compliance to specifications. This method could also be used to implement built-in self-test for phase-locked loops. Experiments with discrete components show the jitter transfer function measuring method is sound.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"254 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113988975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606691
T. Watanabe, Y. Ohtomo, K. Yamakoshi, Y. Takei
This paper presents the routing methodology and CAD tools used in designing Gb/s LSIs with deep submicron technology. A routing method for controlling wire width and spacing is adopted for each net group classified by wire length and the permitted delay constraints. A high-performance router and a high-precision delay analyzer adapted to the methodology have been developed. The methodology has been applied in the design of an ATM-switch LSI using 0.25 /spl mu/m CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s (2.5 Gbps/pin) and an internal clock frequency of 312 MHz.
本文介绍了采用深亚微米技术设计Gb/s级lsi时所采用的布线方法和CAD工具。根据导线长度和允许的时延约束对每一网组进行分类，采用控制导线宽度和间距的布线方法。开发了一种适用于该方法的高性能路由器和高精度延迟分析仪。该方法已应用于采用0.25 /spl μ m CMOS/SIMOX技术的atm开关LSI的设计中。该LSI的吞吐量为40gb /s (2.5 Gbps/pin)，内部时钟频率为312 MHz。
{"title":"An effective routing methodology for Gb/s LSI using deep submicron CMOS/SIMOX technology","authors":"T. Watanabe, Y. Ohtomo, K. Yamakoshi, Y. Takei","doi":"10.1109/CICC.1997.606691","DOIUrl":"https://doi.org/10.1109/CICC.1997.606691","url":null,"abstract":"This paper presents the routing methodology and CAD tools used in designing Gb/s LSIs with deep submicron technology. A routing method for controlling wire width and spacing is adopted for each net group classified by wire length and the permitted delay constraints. A high-performance router and a high-precision delay analyzer adapted to the methodology have been developed. The methodology has been applied in the design of an ATM-switch LSI using 0.25 /spl mu/m CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s (2.5 Gbps/pin) and an internal clock frequency of 312 MHz.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128916850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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