{"title":"High Efficiency & Low Area DC-DC Buck Converter with the Digital Feedback Loop for the Wireless Applications","authors":"H. Jeong, Kangyoon Lee","doi":"10.1109/ICUFN49451.2021.9528400","DOIUrl":null,"url":null,"abstract":"In this Paper, a high efficiency and low area dc-dc buck converter with the digital feedback loop is proposed for wireless device. The digital feedback loop is consisted of two-step digital pulse width modulation (DPWM) and low power self-tracking zero current detector (ST-ZCD). To implement a high-efficiency dc-dc converter, a hybrid DPWM core is proposed with high linearity and low power consumption. To reduce the output voltage ripple within 20mV, an adaptive window analog-to-digital converter is proposed. To minimize the reverse current, a dead time generator is implemented with the proposed ST-ZCD. The circuit is designed with a Samsung 28nm CMOS process that produces an output voltage of 1.8V using a standard supply voltage of 3.3V.","PeriodicalId":318542,"journal":{"name":"2021 Twelfth International Conference on Ubiquitous and Future Networks (ICUFN)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 Twelfth International Conference on Ubiquitous and Future Networks (ICUFN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICUFN49451.2021.9528400","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
In this Paper, a high efficiency and low area dc-dc buck converter with the digital feedback loop is proposed for wireless device. The digital feedback loop is consisted of two-step digital pulse width modulation (DPWM) and low power self-tracking zero current detector (ST-ZCD). To implement a high-efficiency dc-dc converter, a hybrid DPWM core is proposed with high linearity and low power consumption. To reduce the output voltage ripple within 20mV, an adaptive window analog-to-digital converter is proposed. To minimize the reverse current, a dead time generator is implemented with the proposed ST-ZCD. The circuit is designed with a Samsung 28nm CMOS process that produces an output voltage of 1.8V using a standard supply voltage of 3.3V.
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