J.F. Lopez, K. Eshraghian, M.K. McGeever, A. Núñez, R. Sarmiento
{"title":"Gallium arsenide MESFET memory architectures","authors":"J.F. Lopez, K. Eshraghian, M.K. McGeever, A. Núñez, R. Sarmiento","doi":"10.1109/MTDT.1995.518090","DOIUrl":null,"url":null,"abstract":"Gallium arsenide (GaAs) technology, because of its high speed, offers an alternative to silicon (Si). For the particular case of digital memories, speed has great importance taking into account that the success of a high-performance microprocessor depends greatly on how fast data are obtained and sent to memory. However, GaAs presents some problems when implementing memories, mainly due to its leaky characteristics and the small output logic swing compared to that produced in MOS devices. In this paper, novel architectures are proposed in order to overcome these problems. As a result, different designs have been implemented for 2- and 5-kbit ROMs, and for a 14-kbit DRAM.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.1995.518090","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Gallium arsenide (GaAs) technology, because of its high speed, offers an alternative to silicon (Si). For the particular case of digital memories, speed has great importance taking into account that the success of a high-performance microprocessor depends greatly on how fast data are obtained and sent to memory. However, GaAs presents some problems when implementing memories, mainly due to its leaky characteristics and the small output logic swing compared to that produced in MOS devices. In this paper, novel architectures are proposed in order to overcome these problems. As a result, different designs have been implemented for 2- and 5-kbit ROMs, and for a 14-kbit DRAM.
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