Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518087
S. Van Singel, N. Soparkar
Emerging computer applications have unique high-volume data processing and high-performance requirements (e.g. multimedia systems). These requirements are not supported well by standard computer hardware: the major performance degrading factor being the limited memory bandwidth available. To alleviate this problem, we aim to assess and develop the utility of hardware memory enhanced with selected programmable processing capabilities as an alternative to the standard approaches. The key idea is to off-load simple, high-volume data processing to the memory itself in order to reduce the traffic between the processor and the memory units. We consider a simple mathematical model for logic-enhanced memory architectures, and using it, we exhibit the potential gains in performance.
{"title":"Logic-enhanced memories for data-intensive processing","authors":"S. Van Singel, N. Soparkar","doi":"10.1109/MTDT.1995.518087","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518087","url":null,"abstract":"Emerging computer applications have unique high-volume data processing and high-performance requirements (e.g. multimedia systems). These requirements are not supported well by standard computer hardware: the major performance degrading factor being the limited memory bandwidth available. To alleviate this problem, we aim to assess and develop the utility of hardware memory enhanced with selected programmable processing capabilities as an alternative to the standard approaches. The key idea is to off-load simple, high-volume data processing to the memory itself in order to reduce the traffic between the processor and the memory units. We consider a simple mathematical model for logic-enhanced memory architectures, and using it, we exhibit the potential gains in performance.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129053035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518080
M. Hashizume, K. Taga, T. Koyama, T. Tamesada
A large quiescent supply current of mA order flows when a data is written in a CMOS SRAM IC. In this paper, we discuss whether faulty CMOS SRAM ICs, which can not produce the expected outputs, can be detected by measuring quiescent supply currents generated in write operations instead of output logic values. A fault detection method based on the supply current is proposed and is evaluated by some experiments. The method detects 62% of the faulty CMOS SRAM ICs used in the experiments with a small number of test inputs. Also, the total test time can be reduced if the method is used as a pretest method of functional testing. These results suggest that faulty CMOS SRAM ICs can be detected by measuring the supply currents in write operations.
{"title":"CMOS SRAM test based on quiescent supply current in write operation","authors":"M. Hashizume, K. Taga, T. Koyama, T. Tamesada","doi":"10.1109/MTDT.1995.518080","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518080","url":null,"abstract":"A large quiescent supply current of mA order flows when a data is written in a CMOS SRAM IC. In this paper, we discuss whether faulty CMOS SRAM ICs, which can not produce the expected outputs, can be detected by measuring quiescent supply currents generated in write operations instead of output logic values. A fault detection method based on the supply current is proposed and is evaluated by some experiments. The method detects 62% of the faulty CMOS SRAM ICs used in the experiments with a small number of test inputs. Also, the total test time can be reduced if the method is used as a pretest method of functional testing. These results suggest that faulty CMOS SRAM ICs can be detected by measuring the supply currents in write operations.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126888301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518086
L. Nachtergaele, F. Catthoor, F. Balasa, F. Franssen, E. De Greef, H. Samsom, H. de Man
Video and image processing applications deal with large amounts of data which have to be stored and transferred. As the initial system specification describing these data manipulations heavily influences the final memory organization and hierarchy, there is a clear need for exploration support. We believe that the emphasis should lie on fast but accurate estimation and on the high-level steering of the involved system transformations. In this paper, a system exploration environment called ATOMIUM, is presented that supports these requirements. To illustrate the effectiveness of our approach, two realistic demonstrators are worked out and design results are described.
{"title":"Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems","authors":"L. Nachtergaele, F. Catthoor, F. Balasa, F. Franssen, E. De Greef, H. Samsom, H. de Man","doi":"10.1109/MTDT.1995.518086","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518086","url":null,"abstract":"Video and image processing applications deal with large amounts of data which have to be stored and transferred. As the initial system specification describing these data manipulations heavily influences the final memory organization and hierarchy, there is a clear need for exploration support. We believe that the emphasis should lie on fast but accurate estimation and on the high-level steering of the involved system transformations. In this paper, a system exploration environment called ATOMIUM, is presented that supports these requirements. To illustrate the effectiveness of our approach, two realistic demonstrators are worked out and design results are described.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115634819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518090
J.F. Lopez, K. Eshraghian, M.K. McGeever, A. Núñez, R. Sarmiento
Gallium arsenide (GaAs) technology, because of its high speed, offers an alternative to silicon (Si). For the particular case of digital memories, speed has great importance taking into account that the success of a high-performance microprocessor depends greatly on how fast data are obtained and sent to memory. However, GaAs presents some problems when implementing memories, mainly due to its leaky characteristics and the small output logic swing compared to that produced in MOS devices. In this paper, novel architectures are proposed in order to overcome these problems. As a result, different designs have been implemented for 2- and 5-kbit ROMs, and for a 14-kbit DRAM.
{"title":"Gallium arsenide MESFET memory architectures","authors":"J.F. Lopez, K. Eshraghian, M.K. McGeever, A. Núñez, R. Sarmiento","doi":"10.1109/MTDT.1995.518090","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518090","url":null,"abstract":"Gallium arsenide (GaAs) technology, because of its high speed, offers an alternative to silicon (Si). For the particular case of digital memories, speed has great importance taking into account that the success of a high-performance microprocessor depends greatly on how fast data are obtained and sent to memory. However, GaAs presents some problems when implementing memories, mainly due to its leaky characteristics and the small output logic swing compared to that produced in MOS devices. In this paper, novel architectures are proposed in order to overcome these problems. As a result, different designs have been implemented for 2- and 5-kbit ROMs, and for a 14-kbit DRAM.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114375790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518091
W. B. Noghani, I. Jalowiecki
A comprehensive model is developed to estimate yield values for an associative string processor (ASP) chip which is populated with content addressable memory (CAM). The yield model comprises analysis of row and column redundancy strategies for the CAM combined with floor planning of the processor architecture. At the end, a cost model is developed, based on some actual fabrication costs, in order to optimise the processor according to a suitable figure of merit.
{"title":"Yield and cost estimation for a CAM based parallel processor","authors":"W. B. Noghani, I. Jalowiecki","doi":"10.1109/MTDT.1995.518091","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518091","url":null,"abstract":"A comprehensive model is developed to estimate yield values for an associative string processor (ASP) chip which is populated with content addressable memory (CAM). The yield model comprises analysis of row and column redundancy strategies for the CAM combined with floor planning of the processor architecture. At the end, a cost model is developed, based on some actual fabrication costs, in order to optimise the processor according to a suitable figure of merit.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129401225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518089
S. Van Singel, T. Tabe, N. Soparkar, A. Asthana
Applications that involve real-time databases (in which the access to data must satisfy certain time constraints), are difficult to implement on standard architectural platforms. A major reason concerns the limited memory bandwidth available in standard systems which the precludes high performance necessary in "data-intensive" applications. To address this problem, we propose the use of a logic-enhanced memory (hardware memory enhanced with select programmable processing logic) architecture. We describe experimentation with a limited implementation of a real-time database facility for multiprocessors on a logic-enhanced memory system, and our simulations show that such an approach may provide better performance as compared to standard configurations.
{"title":"Performance in real-time main-memory databases","authors":"S. Van Singel, T. Tabe, N. Soparkar, A. Asthana","doi":"10.1109/MTDT.1995.518089","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518089","url":null,"abstract":"Applications that involve real-time databases (in which the access to data must satisfy certain time constraints), are difficult to implement on standard architectural platforms. A major reason concerns the limited memory bandwidth available in standard systems which the precludes high performance necessary in \"data-intensive\" applications. To address this problem, we propose the use of a logic-enhanced memory (hardware memory enhanced with select programmable processing logic) architecture. We describe experimentation with a limited implementation of a real-time database facility for multiprocessors on a logic-enhanced memory system, and our simulations show that such an approach may provide better performance as compared to standard configurations.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124398474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518074
B. Prince
This overview paper discusses sore of the system opportunities and the manufacturing costs of integrating large amounts of logic and memory on a single chip.
本文概述了在单个芯片上集成大量逻辑和存储器的系统机会和制造成本。
{"title":"Challenges in memory-logic integration","authors":"B. Prince","doi":"10.1109/MTDT.1995.518074","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518074","url":null,"abstract":"This overview paper discusses sore of the system opportunities and the manufacturing costs of integrating large amounts of logic and memory on a single chip.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133814573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518085
G.M. Lattimore, M. Kumar, J. M. Poplawski
An experimental 2-cycle, 1-Mbit, 4-way set-associative, 4-way interleave, multiprocessor L2 directory with array access and cycle time equal to 2.5 ns is described. The directory function has three components: (1) address transmission and arbitration around a 17.3/spl times/17.3 chip (/spl sim/1/2 cycle), (2) directory array access (1 full cycle), and (3) tag compare (/spl sim/1/2 cycle). The directory array access design uses a combination of self-resetting and synchronous techniques that allow the array access to span 2 clock cycles even though the array can be pipelined at a single cycle frequency. The combination of synchronous techniques with self-resetting circuits allows the array cycle time to functionally change with the machine cycle time, yielding a greater sense-amplifier margin at longer cycles while maintaining the pipelining benefits of self-resetting circuitry. The process that the design is based upon is a 0.5-micron technology with a 0.25-micron effective gate length and 5 layers of metal. The SRAM cell size is 4.6/spl times/7.2 microns/sup 2/, a full 6-transistor cell with a single layer of poly, and a local area interconnect using a damascene tungsten process. The total directory area is 4 interleaves/spl times/5.6 mm/spl times/5.3 mm = 118.7 mm/sup 2/.
{"title":"A 2 cycle 1 Mbit 4 way set associative 4 way interleave multi-processor L2 directory with array access/cycle 2.5 nsec","authors":"G.M. Lattimore, M. Kumar, J. M. Poplawski","doi":"10.1109/MTDT.1995.518085","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518085","url":null,"abstract":"An experimental 2-cycle, 1-Mbit, 4-way set-associative, 4-way interleave, multiprocessor L2 directory with array access and cycle time equal to 2.5 ns is described. The directory function has three components: (1) address transmission and arbitration around a 17.3/spl times/17.3 chip (/spl sim/1/2 cycle), (2) directory array access (1 full cycle), and (3) tag compare (/spl sim/1/2 cycle). The directory array access design uses a combination of self-resetting and synchronous techniques that allow the array access to span 2 clock cycles even though the array can be pipelined at a single cycle frequency. The combination of synchronous techniques with self-resetting circuits allows the array cycle time to functionally change with the machine cycle time, yielding a greater sense-amplifier margin at longer cycles while maintaining the pipelining benefits of self-resetting circuitry. The process that the design is based upon is a 0.5-micron technology with a 0.25-micron effective gate length and 5 layers of metal. The SRAM cell size is 4.6/spl times/7.2 microns/sup 2/, a full 6-transistor cell with a single layer of poly, and a local area interconnect using a damascene tungsten process. The total directory area is 4 interleaves/spl times/5.6 mm/spl times/5.3 mm = 118.7 mm/sup 2/.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125754043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518093
J. Brzozowski, H. Jurgensen
Single cell-array faults in RAMs are usually represented by Mealy automata. Multiple faults should also be representable by automata; in fact, it should be possible to compute the automaton of a multiple fault from the automata of the single faults that make up the multiple fault. We study properties of binary composition operations on automata for the representation of multiple faults in RAMs. First, we derive a set of generic conditions that every composition operation must satisfy. Second, we develop a set of physical conditions that the composition must satisfy in order to apply to stuck-at, transition and coupling faults in RAMs. Third, we represent the transition table rules used by van de Goor and Smit (1993, 1994) by a composition operation and prove that this operation satisfies both the generic and physical conditions. Fourth, we point out that it may be appropriate to use a different composition operation to permit a different handling of coupling faults in the presence of stuck-at or transition faults.
ram中的单胞阵故障通常用Mealy自动机表示。多个故障也应该用自动机表示;事实上，应该可以从构成多个故障的单个故障的自动机中计算出多个故障的自动机。研究了自动机上二元组合运算的性质，以表示ram中的多个故障。首先，我们推导出一组一般条件，每个复合操作都必须满足这些条件。其次，我们开发了一套物理条件，该组合必须满足，以适用于ram中的卡滞，过渡和耦合故障。第三，我们用复合运算表示van de Goor和Smit(1993,1994)使用的过渡表规则，并证明该运算既满足一般条件又满足物理条件。第四，我们指出，在存在卡滞或转换错误时，使用不同的组合操作来允许对耦合错误进行不同的处理可能是合适的。
{"title":"Composition of multiple faults in RAMs","authors":"J. Brzozowski, H. Jurgensen","doi":"10.1109/MTDT.1995.518093","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518093","url":null,"abstract":"Single cell-array faults in RAMs are usually represented by Mealy automata. Multiple faults should also be representable by automata; in fact, it should be possible to compute the automaton of a multiple fault from the automata of the single faults that make up the multiple fault. We study properties of binary composition operations on automata for the representation of multiple faults in RAMs. First, we derive a set of generic conditions that every composition operation must satisfy. Second, we develop a set of physical conditions that the composition must satisfy in order to apply to stuck-at, transition and coupling faults in RAMs. Third, we represent the transition table rules used by van de Goor and Smit (1993, 1994) by a composition operation and prove that this operation satisfies both the generic and physical conditions. Fourth, we point out that it may be appropriate to use a different composition operation to permit a different handling of coupling faults in the presence of stuck-at or transition faults.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115183593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-07DOI: 10.1109/MTDT.1995.518079
W. Al-Assadi, A. Jayasumana, Y. Malaiya
I/sub DDQ/ (Defect Detection by Quiescent power supply current measurement), or current testing, has emerged in the last few years as an effective technique for detecting certain classes of faults in high-density ICs. In this paper, a testable design that enhances the I/sub DDQ/ testability of static random access memories (SRAMs) for off-line testing as proposed. To achieve high accuracy and a test speed approaching the system operational speed, the memory is partitioned for comparison of I/sub DDQ/ values. Parallel write/read operations are used to activate possible faults, while quiescent power supply currents from two blocks are compared.
{"title":"A bipartite, differential I/sub DDQ/ testable static RAM design","authors":"W. Al-Assadi, A. Jayasumana, Y. Malaiya","doi":"10.1109/MTDT.1995.518079","DOIUrl":"https://doi.org/10.1109/MTDT.1995.518079","url":null,"abstract":"I/sub DDQ/ (Defect Detection by Quiescent power supply current measurement), or current testing, has emerged in the last few years as an effective technique for detecting certain classes of faults in high-density ICs. In this paper, a testable design that enhances the I/sub DDQ/ testability of static random access memories (SRAMs) for off-line testing as proposed. To achieve high accuracy and a test speed approaching the system operational speed, the memory is partitioned for comparison of I/sub DDQ/ values. Parallel write/read operations are used to activate possible faults, while quiescent power supply currents from two blocks are compared.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126225449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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