Coded time-symbolic simulation using shared binary decision diagram

Abstract

A new logic design timing verification technique named coded time-symbolic simulation (CTSS) is presented. Novel techniques of analyzing the results of CTSS are proposed. Simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values is considered. The cases of possible delay values of each gate are encoded by binary values, and all the possible combinations of the delay values are simulated by means of symbolic simulation. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. An efficient simulator was implemented by using a shared binary decision diagram (SBDD) as an internal representation of Boolean functions.<>