An algorithm is introduced which uses logic equations to determine a gate sequence and a set of nets which optimize the gate matrix layout area. Using logic equations allows the reordering of transistors in a completely general manner. Previous works using net-lists and the concept of delayed binding performed only a small subset of the reordering possible with the proposed algorithm. The algorithm has a time complexity of O(E log E) for a design with E equations. The experimental results show a considerable reduction in layout area.<>
介绍了一种利用逻辑方程确定栅极序列和优化栅极矩阵布局面积的一组网的算法。使用逻辑方程可以以完全通用的方式对晶体管进行重新排序。先前使用网络列表和延迟绑定概念的工作仅使用所提出的算法执行了一小部分可能的重新排序。对于有E个方程的设计，该算法的时间复杂度为0 (E log E)。实验结果表明，布局面积明显减小。
{"title":"A transistor reordering technique for gate matrix layout","authors":"U. Singh, C. Y. Chen","doi":"10.1145/123186.123340","DOIUrl":"https://doi.org/10.1145/123186.123340","url":null,"abstract":"An algorithm is introduced which uses logic equations to determine a gate sequence and a set of nets which optimize the gate matrix layout area. Using logic equations allows the reordering of transistors in a completely general manner. Previous works using net-lists and the concept of delayed binding performed only a small subset of the reordering possible with the proposed algorithm. The algorithm has a time complexity of O(E log E) for a design with E equations. The experimental results show a considerable reduction in layout area.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123971399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Casotto, Richard Newton, Albert 0 Sangiovanni-Vincentelli
VOV is an automatic manager for VLSI design. It is based on the idea that CAD tools can leave a trace of their execution. The trace is represented as a bipartite directed and acyclic graph, in which the nodes represent either design data or CAD transactions. By managing and analyzing the traces, VOV offers a wide variety of services related to design management, such as coordination of team design, automatic execution of CAD transactions, and capture of design history and data dependencies. All of these services are provided in a nonintrusive fashion. VOV has the notion of measurement on the design data, an ingredient which is necessary to provide even more services: tracking of design specifications, validation of design data, and design estimation.<>
{"title":"Design management based on design traces","authors":"A. Casotto, Richard Newton, Albert 0 Sangiovanni-Vincentelli","doi":"10.1109/DAC.1990.114843","DOIUrl":"https://doi.org/10.1109/DAC.1990.114843","url":null,"abstract":"VOV is an automatic manager for VLSI design. It is based on the idea that CAD tools can leave a trace of their execution. The trace is represented as a bipartite directed and acyclic graph, in which the nodes represent either design data or CAD transactions. By managing and analyzing the traces, VOV offers a wide variety of services related to design management, such as coordination of team design, automatic execution of CAD transactions, and capture of design history and data dependencies. All of these services are provided in a nonintrusive fashion. VOV has the notion of measurement on the design data, an ingredient which is necessary to provide even more services: tracking of design specifications, validation of design data, and design estimation.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122384158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A problem of memory allocation for intermediate variables in an ASIC synthesis system is addressed. A method is explored of grouping individual memory requirements from a hardware-constrained schedule of an algorithm, such that control and communications may be optimized. A new representation of memory requirements is introduced to explain the method. The technique may also be used to allocate operations to hardware resources. This, and control and communication optimization are illustrated with an example.<>
{"title":"Memory, control and communications synthesis for scheduled algorithms","authors":"D. M. Grant, P. Denyer","doi":"10.1109/DAC.1990.114848","DOIUrl":"https://doi.org/10.1109/DAC.1990.114848","url":null,"abstract":"A problem of memory allocation for intermediate variables in an ASIC synthesis system is addressed. A method is explored of grouping individual memory requirements from a hardware-constrained schedule of an algorithm, such that control and communications may be optimized. A new representation of memory requirements is introduced to explain the method. The technique may also be used to allocate operations to hardware resources. This, and control and communication optimization are illustrated with an example.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120814982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Two tools which facilitate a fault simulation of behavioral models described using the VHSIC hardware description language (VHDL) are presented. The first tool is the behavioral fault mapper (BFM). The BFM algorithm accepts a fault-free VHDL model and a fault-list of N faults from which it produces N faulty models. The process of mapping the faults in the fault-list onto copies of the original VHDL model is automated. The N faulty models are immediately suitable for fault simulation. The second tool presented is test bench generator (TBG). The TBG algorithm creates the VHDL testbench and all other files necessary to complete a batch-mode fault simulation of the N faulty models.<>
{"title":"Behavioral fault simulation in VHDL","authors":"P. C. Ward, J. Armstrong","doi":"10.1109/DAC.1990.114922","DOIUrl":"https://doi.org/10.1109/DAC.1990.114922","url":null,"abstract":"Two tools which facilitate a fault simulation of behavioral models described using the VHSIC hardware description language (VHDL) are presented. The first tool is the behavioral fault mapper (BFM). The BFM algorithm accepts a fault-free VHDL model and a fault-list of N faults from which it produces N faulty models. The process of mapping the faults in the fault-list onto copies of the original VHDL model is automated. The N faulty models are immediately suitable for fault simulation. The second tool presented is test bench generator (TBG). The TBG algorithm creates the VHDL testbench and all other files necessary to complete a batch-mode fault simulation of the N faulty models.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123769842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel approach to the automatic layout synthesis of dynamic CMOS circuits is presented. A set of logic expressions is realized in a row of cells. Taking multi-level Boolean expressions as input, logic transistors are placed and routed. Efficient solutions are achieved by permitting the variables of the expressions and by row folding. The layout is designed on a coarse grid taking timing requirements into account and afterwards adapted to the geometric design rules by a compactor. A comparison to handcrafted layouts shows that the results of PALACE are nearly equivalent, while the design productivity is significantly increased.<>
{"title":"PALACE: a layout generator for SCVS logic blocks","authors":"K. M. Just, E. Auer, W. Schiele, A. Schwaferts","doi":"10.1109/DAC.1990.114901","DOIUrl":"https://doi.org/10.1109/DAC.1990.114901","url":null,"abstract":"A novel approach to the automatic layout synthesis of dynamic CMOS circuits is presented. A set of logic expressions is realized in a row of cells. Taking multi-level Boolean expressions as input, logic transistors are placed and routed. Efficient solutions are achieved by permitting the variables of the expressions and by row folding. The layout is designed on a coarse grid taking timing requirements into account and afterwards adapted to the geometric design rules by a compactor. A comparison to handcrafted layouts shows that the results of PALACE are nearly equivalent, while the design productivity is significantly increased.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122724613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cell synthesis is the process of turning a netlist into an efficient IC layout without being restricted to a library of predesigned cells or a fixed floorplan. Normally, this job is broken into at least three parts: placement, routing, and detailed cell generation. Each of these tasks is often divided further into a global and a detailed phase. A cell synthesis system, called sea of devices (SOD), is presented with emphasis on its routing phase. In particular, SOD uses a new model for the global routing problem. This model is based on traditional Steiner trees, but includes detailed geometric information specific to the cell synthesis problem. The system models diffusion strips, congestion, and existing feedthroughs as a cost function associated with regions on the routing plane. A sequence of algorithms based on spanning trees. Steiner trees, maze routing, and channel routing techniques is used to find solutions that make use of this detailed knowledge. The presentation includes some discussion of the algorithms that tie the routing phases together and illustrates the underlying support structures, which are needed for efficient access.<>
{"title":"Global routing considerations in a cell synthesis system","authors":"D. Hill, D. Shugard","doi":"10.1109/DAC.1990.114872","DOIUrl":"https://doi.org/10.1109/DAC.1990.114872","url":null,"abstract":"Cell synthesis is the process of turning a netlist into an efficient IC layout without being restricted to a library of predesigned cells or a fixed floorplan. Normally, this job is broken into at least three parts: placement, routing, and detailed cell generation. Each of these tasks is often divided further into a global and a detailed phase. A cell synthesis system, called sea of devices (SOD), is presented with emphasis on its routing phase. In particular, SOD uses a new model for the global routing problem. This model is based on traditional Steiner trees, but includes detailed geometric information specific to the cell synthesis problem. The system models diffusion strips, congestion, and existing feedthroughs as a cost function associated with regions on the routing plane. A sequence of algorithms based on spanning trees. Steiner trees, maze routing, and channel routing techniques is used to find solutions that make use of this detailed knowledge. The presentation includes some discussion of the algorithms that tie the routing phases together and illustrates the underlying support structures, which are needed for efficient access.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114454165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Edmond, Anurag P. Gupta, D. Siewiorek, Audrey A. Brennan
Describes ASSURE, an automated design-for-dependability advisor, which is a part of the MICON system for rapid prototyping of small computer systems. A design-for-dependability methodology and a formal interface between synthesis and dependability analysis are presented. ASSURE's operation includes dependability analysis, evaluation of dependability enhancement techniques using predictive estimation, and selection of a technique. Different kinds of knowledge used in designing for dependability are identified, including an algorithmic approach for dependability analysis and a knowledge-based approach for suggesting dependability enhancement techniques. Examples of designs produced using ASSURE as a dependability advisor are provided and show an order of magnitude dependability improvement.<>
{"title":"ASSURE: automated design for dependability","authors":"P. Edmond, Anurag P. Gupta, D. Siewiorek, Audrey A. Brennan","doi":"10.1109/DAC.1990.114917","DOIUrl":"https://doi.org/10.1109/DAC.1990.114917","url":null,"abstract":"Describes ASSURE, an automated design-for-dependability advisor, which is a part of the MICON system for rapid prototyping of small computer systems. A design-for-dependability methodology and a formal interface between synthesis and dependability analysis are presented. ASSURE's operation includes dependability analysis, evaluation of dependability enhancement techniques using predictive estimation, and selection of a technique. Different kinds of knowledge used in designing for dependability are identified, including an algorithmic approach for dependability analysis and a knowledge-based approach for suggesting dependability enhancement techniques. Examples of designs produced using ASSURE as a dependability advisor are provided and show an order of magnitude dependability improvement.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129416754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Proposes a graph-theoretic approach for the data path allocation problem. The problem is decomposed into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian method. The third subproblem is solved using a greedy method. It is shown that, by taking the other into consideration while solving one, equally satisfactory results can be obtained, regardless of the order in which (1) and (2) are performed. Two programs, LYRA and ARYL, are implemented which solve the subtasks in different orders. For register allocation, the approach is the first one to guarantee minimal use of registers while being able to take the interconnection cost into account. This research has demonstrated that the bipartite weighted matching algorithm is indeed a good solution for the data path allocation problem.<>
{"title":"Data path allocation based on bipartite weighted matching","authors":"Chu-Yi Huang, Yen-Shen Chen, Y. Lin, Y. Hsu","doi":"10.1109/DAC.1990.114907","DOIUrl":"https://doi.org/10.1109/DAC.1990.114907","url":null,"abstract":"Proposes a graph-theoretic approach for the data path allocation problem. The problem is decomposed into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian method. The third subproblem is solved using a greedy method. It is shown that, by taking the other into consideration while solving one, equally satisfactory results can be obtained, regardless of the order in which (1) and (2) are performed. Two programs, LYRA and ARYL, are implemented which solve the subtasks in different orders. For register allocation, the approach is the first one to guarantee minimal use of registers while being able to take the interconnection cost into account. This research has demonstrated that the bipartite weighted matching algorithm is indeed a good solution for the data path allocation problem.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128310944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An algorithm, called EST, is presented which is a new combinatorial automatic test-pattern generation (ATPG) branch-and-bound search algorithm, based on the generation of equivalent logic decompositions (search states) at each search decision point. The E-frontier is an efficient representation of a search state and is used with a hashing algorithm to detect equivalent search states. When EST matches an equivalent search state from a prior fault, and both prior and current faults are sensitized, EST completes the current fault test-pattern with values from the prior fault test-pattern and terminates search immediately. A new method of redundant fault analysis is also introduced that uniquely determines signal values for subsequent test-pattern search. Results show that this algorithm accelerates the base ATPG algorithm by a factor of 1.03 to 328 when considering all faults, a factor of 1347:1 for hard-to-test faults and a factor of 200000 for certain redundancy proofs for the test cases shown.<>
{"title":"EST: the new frontier in automatic test-pattern generation","authors":"J. Giraldi, M. Bushnell","doi":"10.1109/DAC.1990.114937","DOIUrl":"https://doi.org/10.1109/DAC.1990.114937","url":null,"abstract":"An algorithm, called EST, is presented which is a new combinatorial automatic test-pattern generation (ATPG) branch-and-bound search algorithm, based on the generation of equivalent logic decompositions (search states) at each search decision point. The E-frontier is an efficient representation of a search state and is used with a hashing algorithm to detect equivalent search states. When EST matches an equivalent search state from a prior fault, and both prior and current faults are sensitized, EST completes the current fault test-pattern with values from the prior fault test-pattern and terminates search immediately. A new method of redundant fault analysis is also introduced that uniquely determines signal values for subsequent test-pattern search. Results show that this algorithm accelerates the base ATPG algorithm by a factor of 1.03 to 328 when considering all faults, a factor of 1347:1 for hard-to-test faults and a factor of 200000 for certain redundancy proofs for the test cases shown.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121407329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A single high-level synthesis algorithm is presented that schedules the operations of a data dependence graph, allocates the necessary hardware and maps the operations to specific functional units. This is achieved by extending the global analysis approach developed for force-directed scheduling to include individual module instances. This new algorithm should be applicable to any behavioral synthesis system that schedules operations from a data dependence graph.<>
{"title":"The combination of scheduling, allocation, and mapping in a single algorithm","authors":"R. J. Cloutier, D. E. Thomas","doi":"10.1109/DAC.1990.114832","DOIUrl":"https://doi.org/10.1109/DAC.1990.114832","url":null,"abstract":"A single high-level synthesis algorithm is presented that schedules the operations of a data dependence graph, allocates the necessary hardware and maps the operations to specific functional units. This is achieved by extending the global analysis approach developed for force-directed scheduling to include individual module instances. This new algorithm should be applicable to any behavioral synthesis system that schedules operations from a data dependence graph.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121526272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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