{"title":"The VHDL validation suite","authors":"J. Armstrong, C. Cho, Sandeep Shah, C. Kosaraju","doi":"10.1109/DAC.1990.114819","DOIUrl":null,"url":null,"abstract":"A validation suite for the IEEE standard VHSIC Hardware Description Language (VHDL) is discussed along with its executive manager. Test points are generated from the VHDL LRM (language reference manual) syntax diagrams and sentences. Each test in the suite contains a test header which is specially formatted and keeps information such as test point, test objective, test result, and test type. The suit executive manager is menu-driven and efficiently classifies the tests based on different criterion defined in the test header. Coverage is defined to measure how closely a VHDL tool covers the LRM and is also computed by the suite executive manager.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1990.114819","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A validation suite for the IEEE standard VHSIC Hardware Description Language (VHDL) is discussed along with its executive manager. Test points are generated from the VHDL LRM (language reference manual) syntax diagrams and sentences. Each test in the suite contains a test header which is specially formatted and keeps information such as test point, test objective, test result, and test type. The suit executive manager is menu-driven and efficiently classifies the tests based on different criterion defined in the test header. Coverage is defined to measure how closely a VHDL tool covers the LRM and is also computed by the suite executive manager.<>
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
