Programming paradigm of a microcontroller with hardware scheduler engine and independent pipeline registers - a software approach

Abstract

In computer science, for embedded field only two types of microcontrollers exists, that can be used to develop a working system. You can use a single core or a multicore which is much faster but will not be the equivalent of a single core multiple with the numbers of cores, because a small part from the power will be used for inter process communications. Our approach is a little bit different because we use a single core CPU that have a number of finite task that act like different CPU's. In this new architecture there is no need for inter process communication because the processor is a single core and the hardware tasks use the same resources as others. The peripherals of this architecture will improve interrupt latencies and task switching times, what makes this microcontroller the best choice when it comes in interrupt response time.