Designing an accelerated hardware architecture for polynomial matrix multiplications

Abstract

In this project, reconfigurable hardware architecture is used for performing the polynomial matrix multiplications (PMM). Hardware architecture is designed by using the Xilinx system generator tool. System generator enables the use of the math works model-based Simulink design environment for FPGA design. For designing PMM system, Fast Fourier Transform (FFT) technique is used rather than Convolution technique, because convolution takes computational time more than FFT. It's easy to implement the generic structure of FFT. This project implements the sharpening, smoothing, blurring and Gaussian smooth application using polynomial matrix multiplication. The hardware implementation is possible by using field-programmable array architecture. This PMM system takes less time for execution and it uses less FPGA resources like number of slice registers, number of slice LUT's, the number of block RAM/FIFO and number of bonded IOBs. The architecture for computing the PMM is implemented on Virtex-5.