Efficient digital baseline wander algorithm and its architecture for fast Ethernet

Abstract

The paper proposes an efficient digital baseline wander (BLW) algorithm and its hardware architecture for 100BASE-TX Ethernet. The proposed BLW compensator uses four symbols, including the present symbol, and can remove BLW at the channel having large BLW or having a killing packet. The proposed BLW compensator is purely implemented in a digital domain. To verify the performance of the proposed BLW compensator, we simulate a 100BASE-TX DSP submodule using the SPW/spl trade/ tool. The DSP submodule has been modeled by Verilog-HDL and synthesized using the 0.18 /spl mu/m SEC cell library. The measured BER is less than 10/sup -10/ when the transmitted data is received up to 150 m. The implemented DSP submodule operates at 142.7 MHz and consists of 128,528 gates. Since the 1000Base-T receiver uses DSP submodule similar to 100BASE-TX receiver, the proposed architecture can be reused for gigabit Ethernet.