Pub Date : 2004-12-06DOI: 10.1109/SIPS.2004.1363018
B. Bougard, S. Pollin, G. Lenoir, L. V. D. Perre, F. Catthoor, Wim Dehaene
Next generation wireless local area network (WLAN) terminals have to cope with increasing performance requirements while energy budgets are more and more constrained by portability. Next to low power circuit and architecture design, system-level power management is a key technology to fill this gap. Recently, radio link control techniques have been proposed, not only as a way to maximize performance but also to reach energy awareness. Transmit rate and power are adapted to meet exactly the user requirements while minimizing the average power consumption. However, schemes proposed so far do not exploit the characteristics of the specific modulation scheme considered in most recent WLAN standards: orthogonal frequency division multiplexing (OFDM). In this paper, we design a practical energy aware radio link control scheme, optimized for OFDM transceivers and compatible with current standards. Simulation results depict up to 80% transceiver power reduction when compared with throughput maximizing schemes.
{"title":"Energy-aware radio link control for OFDM-based WLAN","authors":"B. Bougard, S. Pollin, G. Lenoir, L. V. D. Perre, F. Catthoor, Wim Dehaene","doi":"10.1109/SIPS.2004.1363018","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363018","url":null,"abstract":"Next generation wireless local area network (WLAN) terminals have to cope with increasing performance requirements while energy budgets are more and more constrained by portability. Next to low power circuit and architecture design, system-level power management is a key technology to fill this gap. Recently, radio link control techniques have been proposed, not only as a way to maximize performance but also to reach energy awareness. Transmit rate and power are adapted to meet exactly the user requirements while minimizing the average power consumption. However, schemes proposed so far do not exploit the characteristics of the specific modulation scheme considered in most recent WLAN standards: orthogonal frequency division multiplexing (OFDM). In this paper, we design a practical energy aware radio link control scheme, optimized for OFDM transceivers and compatible with current standards. Simulation results depict up to 80% transceiver power reduction when compared with throughput maximizing schemes.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115342113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/SIPS.2004.1363042
Sizhong Chen, Tong Zhang
Most pipelined adaptive signal processing systems are inherently subject to a trade-off between throughput and signal processing performance because of the adaptation feedback loops. To mitigate this dilemma, we propose to apply an asynchronous pipeline to implement pipelined adaptive signal processing systems that can support run-time reconfigurable throughput/performance trade-offs. This can be leveraged to improve the overall system performance in many applications. In this work, we demonstrate this design approach using a delayed LMS (DLMS) adaptive decision feedback equalizer (ADFE) for the communication links with variable data rate. By adjusting the pipelining depth on-the-fly, the DLMS ADFE can dynamically track the best equalization performance allowed by different data rates. We develop the design scheme that applies a zero-delay-overhead asynchronous pipeline style to implement ADFE and support dynamic pipelining depth control. Simulation result shows a significant performance improvement compared with its synchronous counterpart.
{"title":"Run-time reconfigurable adaptive signal processing system with asynchronous dynamic pipelining: a case study of DLMS ADFE","authors":"Sizhong Chen, Tong Zhang","doi":"10.1109/SIPS.2004.1363042","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363042","url":null,"abstract":"Most pipelined adaptive signal processing systems are inherently subject to a trade-off between throughput and signal processing performance because of the adaptation feedback loops. To mitigate this dilemma, we propose to apply an asynchronous pipeline to implement pipelined adaptive signal processing systems that can support run-time reconfigurable throughput/performance trade-offs. This can be leveraged to improve the overall system performance in many applications. In this work, we demonstrate this design approach using a delayed LMS (DLMS) adaptive decision feedback equalizer (ADFE) for the communication links with variable data rate. By adjusting the pipelining depth on-the-fly, the DLMS ADFE can dynamically track the best equalization performance allowed by different data rates. We develop the design scheme that applies a zero-delay-overhead asynchronous pipeline style to implement ADFE and support dynamic pipelining depth control. Simulation result shows a significant performance improvement compared with its synchronous counterpart.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115713762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/SIPS.2004.1363067
E. Fung, K. Leung, N. Parimi, M. Purnaprajna, V. Gaudet
A design for a white Gaussian noise generator (WGNG) is modified and implemented as a 0.18-/spl mu/m CMOS digital ASIC for high-speed communication channel emulation. The original design was implemented using an FPGA. The goal of the work presented is to enhance the performance of the WGNG in order to achieve emulation of high-speed communication standards unattainable by the FPGA implementation. This is accomplished by pipelining the original design and implementing it using an ASIC. A layout is generated, based on a standard digital design flow provided by the Canadian Microelectronics Corporation (CMC). This implementation achieves an output rate of 182 Msamples/sec, which exceeds the speed of the original FPGA implementation by more than seven times.
对高斯白噪声发生器(WGNG)的设计进行了改进，并将其实现为0.18-/spl μ m CMOS数字专用集成电路，用于高速通信信道仿真。最初的设计是使用FPGA实现的。提出的工作目标是提高WGNG的性能，以实现FPGA实现无法实现的高速通信标准的仿真。这是通过将原始设计流水线化并使用ASIC来实现的。根据加拿大微电子公司(CMC)提供的标准数字设计流程生成布局。该实现实现了182 m采样/秒的输出速率，超过了原始FPGA实现速度的7倍以上。
{"title":"ASIC implementation of a high speed WGNG for communication channel emulation [white Gaussian noise generator]","authors":"E. Fung, K. Leung, N. Parimi, M. Purnaprajna, V. Gaudet","doi":"10.1109/SIPS.2004.1363067","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363067","url":null,"abstract":"A design for a white Gaussian noise generator (WGNG) is modified and implemented as a 0.18-/spl mu/m CMOS digital ASIC for high-speed communication channel emulation. The original design was implemented using an FPGA. The goal of the work presented is to enhance the performance of the WGNG in order to achieve emulation of high-speed communication standards unattainable by the FPGA implementation. This is accomplished by pipelining the original design and implementing it using an ASIC. A layout is generated, based on a standard digital design flow provided by the Canadian Microelectronics Corporation (CMC). This implementation achieves an output rate of 182 Msamples/sec, which exceeds the speed of the original FPGA implementation by more than seven times.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120944191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/SIPS.2004.1363059
M. Shaaban, S. Goel, M. Bayoumi
The paper presents an algorithmic enhancement of the full-search block-matching algorithm for motion estimation for real-time systems. The multi-stage interval based motion estimation (MIME) algorithm reduces the computational load by successively eliminating candidate blocks from the search window. The elimination process uses low bit-resolution and it is applied in multiple stages for motion vector computation. On average, MIME eliminates more than 88% of the candidate blocks in the search window after the first and second stage. Based on these results, in a real-time environment, the algorithm can be stopped at any stage without incurring significant loss in motion estimation accuracy. Simulation results show that, in the worst case scenario when the algorithm stops after first stage, there is an average loss of only 3 dB in PSNR as compared to the full-search block-matching algorithm and an average loss of 1.2 dB if the algorithm is stopped after the second step.
{"title":"Motion estimation algorithm for real-time systems","authors":"M. Shaaban, S. Goel, M. Bayoumi","doi":"10.1109/SIPS.2004.1363059","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363059","url":null,"abstract":"The paper presents an algorithmic enhancement of the full-search block-matching algorithm for motion estimation for real-time systems. The multi-stage interval based motion estimation (MIME) algorithm reduces the computational load by successively eliminating candidate blocks from the search window. The elimination process uses low bit-resolution and it is applied in multiple stages for motion vector computation. On average, MIME eliminates more than 88% of the candidate blocks in the search window after the first and second stage. Based on these results, in a real-time environment, the algorithm can be stopped at any stage without incurring significant loss in motion estimation accuracy. Simulation results show that, in the worst case scenario when the algorithm stops after first stage, there is an average loss of only 3 dB in PSNR as compared to the full-search block-matching algorithm and an average loss of 1.2 dB if the algorithm is stopped after the second step.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114560897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/SIPS.2004.1363049
H. Choo, K. Roy
In this paper, a joint control methodology of error protection capability and modulation strategy is presented to minimize the energy dissipation of a given communication. The communication energy includes the energy consumption of the underlying digital (channel encoder/decoder) and analog blocks including the RF amplifier. The energy dissipation of these blocks is determined by the system configuration parameters like channel coding rate, modulation order, transmission power and transmission duration. Simulation was performed on various channel qualities using the Nakagami channel model. The simulation results show that the jointly controlled communication system enhances energy efficiency. When the Nakagami fading figure is 6, 25% of the energy can be saved on average from a QPSK system with channel coding rate of 0.5. The configuration of the system should be determined considering channel quality (fading and path loss).
{"title":"A parametric approach for low energy wireless data communication [mobile multimedia computing/communication applications]","authors":"H. Choo, K. Roy","doi":"10.1109/SIPS.2004.1363049","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363049","url":null,"abstract":"In this paper, a joint control methodology of error protection capability and modulation strategy is presented to minimize the energy dissipation of a given communication. The communication energy includes the energy consumption of the underlying digital (channel encoder/decoder) and analog blocks including the RF amplifier. The energy dissipation of these blocks is determined by the system configuration parameters like channel coding rate, modulation order, transmission power and transmission duration. Simulation was performed on various channel qualities using the Nakagami channel model. The simulation results show that the jointly controlled communication system enhances energy efficiency. When the Nakagami fading figure is 6, 25% of the energy can be saved on average from a QPSK system with channel coding rate of 0.5. The configuration of the system should be determined considering channel quality (fading and path loss).","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129825957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/SIPS.2004.1363033
D. Hocevar
We apply layered belief propagation decoding to our previously devised irregular partitioned permutation LDPC codes. These codes have a construction that easily accommodates a layered decoding and we show that the decoding performance is improved by a factor of two in the number of iterations required. We show how our previous flexible decoding architecture can be adapted to facilitate layered decoding. This results in a significant reduction in the number of memory bits and memory instances required, in the range of 45-50%. The faster decoding speed means the decoder logic can also be reduced by nearly 50% to achieve the same throughput and error performance. In total, the overall decoder architecture can be reduced by nearly 50%.
{"title":"A reduced complexity decoder architecture via layered decoding of LDPC codes","authors":"D. Hocevar","doi":"10.1109/SIPS.2004.1363033","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363033","url":null,"abstract":"We apply layered belief propagation decoding to our previously devised irregular partitioned permutation LDPC codes. These codes have a construction that easily accommodates a layered decoding and we show that the decoding performance is improved by a factor of two in the number of iterations required. We show how our previous flexible decoding architecture can be adapted to facilitate layered decoding. This results in a significant reduction in the number of memory bits and memory instances required, in the range of 45-50%. The faster decoding speed means the decoder logic can also be reduced by nearly 50% to achieve the same throughput and error performance. In total, the overall decoder architecture can be reduced by nearly 50%.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121007707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/sips.2004.1363063
Fan-Min Li, P. Shen, A. Wu
To satisfy the advanced FEC standard that performs both convolutional coding and turbo coding, a unified convolutional/turbo decoder is needed. The timing of both Viterbi and MAP algorithms are analyzed. We introduce three techniques, including interleaving, pointer, and parallel schemes, which can be used in timing charts to reduce memory or increase throughput. In recent works, several timing charts of VA or MAP have been presented, but there is no combined timing analysis of both algorithms. We propose two types of triple-mode MAP/VA timing charts by complementing the idle times of each other.
{"title":"Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design","authors":"Fan-Min Li, P. Shen, A. Wu","doi":"10.1109/sips.2004.1363063","DOIUrl":"https://doi.org/10.1109/sips.2004.1363063","url":null,"abstract":"To satisfy the advanced FEC standard that performs both convolutional coding and turbo coding, a unified convolutional/turbo decoder is needed. The timing of both Viterbi and MAP algorithms are analyzed. We introduce three techniques, including interleaving, pointer, and parallel schemes, which can be used in timing charts to reduce memory or increase throughput. In recent works, several timing charts of VA or MAP have been presented, but there is no combined timing analysis of both algorithms. We propose two types of triple-mode MAP/VA timing charts by complementing the idle times of each other.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121914228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/SIPS.2004.1363017
Alok Aggarwal, Teresa H. Meng
This paper describes an efficient convex optimization technique for computing the globally optimal tradeoff curves between OFDM peak-to-average power ratio (PAR), constellation error, and free carrier power. The OFDM system designer can select a suitable PAR reduction method by comparing the achieved performance of various algorithms with these optimal tradeoff curves. Simulation results are presented for the 802.11a/g WLAN standard. The power wasted in the free carriers can be substantially reduced by taking advantage of the allowed constellation error and by backing off 1 dB from the globally minimum PAR. A convex interior-point method reaches the desired tradeoff point within two iterations for both QPSK and 64-QAM.
{"title":"Globally optimal tradeoff curves for OFDM PAR reduction [peak-to-average power ratio]","authors":"Alok Aggarwal, Teresa H. Meng","doi":"10.1109/SIPS.2004.1363017","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363017","url":null,"abstract":"This paper describes an efficient convex optimization technique for computing the globally optimal tradeoff curves between OFDM peak-to-average power ratio (PAR), constellation error, and free carrier power. The OFDM system designer can select a suitable PAR reduction method by comparing the achieved performance of various algorithms with these optimal tradeoff curves. Simulation results are presented for the 802.11a/g WLAN standard. The power wasted in the free carriers can be substantially reduced by taking advantage of the allowed constellation error and by backing off 1 dB from the globally minimum PAR. A convex interior-point method reaches the desired tradeoff point within two iterations for both QPSK and 64-QAM.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131892464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/SIPS.2004.1363076
W. Chelton, M. Benaissa
This paper proposes a new architecture for an arithmetic unit (AU) for applications that operate over GF(2/sup m/), in particular elliptic curve cryptography. The AU is completely scalable enabling it to operate over any field degree without the need to reconfigure hardware. Operands are considered as a series of w-bit words, where w can be set to meet design requirements. By transferring the complexity of control to software, whilst retaining the generic functions of division and multiplication in hardware, a low area, highly flexible implementation can be attained. A proof-of concept AU was implemented and tested in FPGA. Theoretical results were calculated for scalar multiplication, which were compared to a less scalable implementation. Though the AU cannot achieve the computational speed attained by the other implementation it offers potentially large improvements when considering the area-time product and, therefore, improved efficiency.
{"title":"A scalable GF(2/sup m/) arithmetic unit for application in an ECC processor","authors":"W. Chelton, M. Benaissa","doi":"10.1109/SIPS.2004.1363076","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363076","url":null,"abstract":"This paper proposes a new architecture for an arithmetic unit (AU) for applications that operate over GF(2/sup m/), in particular elliptic curve cryptography. The AU is completely scalable enabling it to operate over any field degree without the need to reconfigure hardware. Operands are considered as a series of w-bit words, where w can be set to meet design requirements. By transferring the complexity of control to software, whilst retaining the generic functions of division and multiplication in hardware, a low area, highly flexible implementation can be attained. A proof-of concept AU was implemented and tested in FPGA. Theoretical results were calculated for scalar multiplication, which were compared to a less scalable implementation. Though the AU cannot achieve the computational speed attained by the other implementation it offers potentially large improvements when considering the area-time product and, therefore, improved efficiency.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128911589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/SIPS.2004.1363039
Chul Y. Jung, M. Sunwoo, Seong K. Oh
This paper proposes a reconfigurable coprocessor for communication systems, which can support high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc., and it can be used for next generation communication platforms to satisfy high speed operations. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 /spl mu/m standard cell library. The gate count is about 35,000 and the critical path is 3.84 ns with the 0.18 /spl mu/m technology. The proposed coprocessor shows performance improvements compared with existing DSP chips for communication algorithms.
{"title":"Design of reconfigurable coprocessor for communication systems","authors":"Chul Y. Jung, M. Sunwoo, Seong K. Oh","doi":"10.1109/SIPS.2004.1363039","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363039","url":null,"abstract":"This paper proposes a reconfigurable coprocessor for communication systems, which can support high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc., and it can be used for next generation communication platforms to satisfy high speed operations. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 /spl mu/m standard cell library. The gate count is about 35,000 and the critical path is 3.84 ns with the 0.18 /spl mu/m technology. The proposed coprocessor shows performance improvements compared with existing DSP chips for communication algorithms.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117262973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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