A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR

Sang-Min Yoo, Tae-Hwan Oh, J. Moon, Seunghoon Lee, U. Moon
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引用次数: 32

Abstract

A 10 b multibit-per-stage pipelined ADC incorporating the merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25 /spl mu/m CMOS process, occupies 3.6 mm/sup 2/ active die area and consumes 208 mW under a 2.5 V power supply.
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具有高SFDR的2.5 V 10 b 120 MSample/s CMOS流水线ADC
采用合并电容开关(MCS)技术的10 b多比特/级流水线ADC在120 MSample/s下可实现53 dB SNDR,在输入频率高达奈奎斯特的100 MSample/s下可实现54 dB SNDR和68 dB SFDR。测得的DNL和INL分别为/spl plusmn/0.40 LSB和/spl plusmn/0.48 LSB。该ADC采用0.25 /spl μ m CMOS工艺制造,占用3.6 mm/sup / /有源芯片面积,在2.5 V电源下功耗为208 mW。
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