Ultra-thin silicon dioxide leakage current and scaling limit

Abstract

Modifications are made to Fowler-Nordheim tunneling current analysis to model accurately the measured conduction characteristics of insulator layers thinner than 6 nm. The most significant is direct tunneling for which a closed-form expression is introduced. Polysilicon depletion and electron wave interference are also considered. 4 nm is found to a practical limit for SiO/sub 2/ scaling in VLSI applications due to direct tunneling leakage almost independent of power supply voltage. The convergence of the intrinsic TDDB and gate leakage criteria is established and the possibility that gate leakage will set the ultimate limit to oxide scaling at 4 nm is suggested.<>