Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200660
T. Shibata, T. Ohmi
A functional MOS transistor called a neuron MOSFET (vMOS) which simulates the function of biological neurons is discussed. A method of constructing neural network LSIs that have a self-learning capability using the neuron MOSFET is given. The key is the implementation of a synaptic connection which changes its weight according to various learning algorithms. In addition, the synapse must be free from standby power dissipation and be as small as possible.<>
{"title":"A self-learning neural-network LSI using neuron MOSFETs","authors":"T. Shibata, T. Ohmi","doi":"10.1109/VLSIT.1992.200660","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200660","url":null,"abstract":"A functional MOS transistor called a neuron MOSFET (vMOS) which simulates the function of biological neurons is discussed. A method of constructing neural network LSIs that have a self-learning capability using the neuron MOSFET is given. The key is the implementation of a synaptic connection which changes its weight according to various learning algorithms. In addition, the synapse must be free from standby power dissipation and be as small as possible.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121067234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200652
N. Matsunaga, H. Shibata, K. Hashimoto
A study to characterize the electromigration behavior in quarter-micron lines is discussed. An increase of activation energy (E/sub a/) with reduction of line width has been experimentally observed. It was also found that there is a region where the lifetime degrades in spite of an increase in E/sub a/ as line width is reduced. This degradation is caused by current crowding and joule-heating around voids that exist before current stressing. According to the electromigration model, a larger grain size and higher
{"title":"Influence of stress-induced void formation on electromigration endurance in quarter-micron aluminum interconnects","authors":"N. Matsunaga, H. Shibata, K. Hashimoto","doi":"10.1109/VLSIT.1992.200652","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200652","url":null,"abstract":"A study to characterize the electromigration behavior in quarter-micron lines is discussed. An increase of activation energy (E/sub a/) with reduction of line width has been experimentally observed. It was also found that there is a region where the lifetime degrades in spite of an increase in E/sub a/ as line width is reduced. This degradation is caused by current crowding and joule-heating around voids that exist before current stressing. According to the electromigration model, a larger grain size and higher","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125155798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200620
D. Kenney, P. Parries, P. Pan, W. Tonti, W. Cote, S. Dash, P. Lorenz, W. Arden, R. Mohler, S. Roehl, A. Bryant, W. Haensch, B. Hoffmann, M. Levy, A. Yu, C. Zeller
A technology for fabricating a 64-Mb DRAM is described. The basic cell concept is an evolution from IBM's SPT cell and a modified SPT cell. Ground-rule shrinkage and additional features permit the realization of a cell size of 1.5 mu m/sup 2/. The chip incorporates N-array transfer gates isolated from the P-substrate by an intervening buried N-layer which forms the buried plate for the trench capacitor. The N-array devices, isolated P-well, and low-resistance wordline conductors provide a dense cell with superior soft-error-rate (SER) protection. Density improvement is achieved by the use of fully borderless contacts and ground-rule shrinkage. The interconnects use a Damascene metallization scheme that repeatedly applies chemical-mechanical polishes for dielectrics and metals.<>
{"title":"A buried-plate trench cell for a 64-Mb DRAM","authors":"D. Kenney, P. Parries, P. Pan, W. Tonti, W. Cote, S. Dash, P. Lorenz, W. Arden, R. Mohler, S. Roehl, A. Bryant, W. Haensch, B. Hoffmann, M. Levy, A. Yu, C. Zeller","doi":"10.1109/VLSIT.1992.200620","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200620","url":null,"abstract":"A technology for fabricating a 64-Mb DRAM is described. The basic cell concept is an evolution from IBM's SPT cell and a modified SPT cell. Ground-rule shrinkage and additional features permit the realization of a cell size of 1.5 mu m/sup 2/. The chip incorporates N-array transfer gates isolated from the P-substrate by an intervening buried N-layer which forms the buried plate for the trench capacitor. The N-array devices, isolated P-well, and low-resistance wordline conductors provide a dense cell with superior soft-error-rate (SER) protection. Density improvement is achieved by the use of fully borderless contacts and ground-rule shrinkage. The interconnects use a Damascene metallization scheme that repeatedly applies chemical-mechanical polishes for dielectrics and metals.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"545 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116229496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200623
S. Chiang, R. Wang, T. Speers, J. Mccollum, E. Hamdy, C. Hu
Cross-section TEM photos that capture the conductive channel of oxide-nitride-oxide (ONO) films after electric breakdown are discussed. The photos reveal a single crystal or polycrystal channel with a dome-shaped cap depending on the breakdown current. The implications of this structure for electric characteristics is analyzed with a spherical thermal-electric model. When ONO films are used as antifuse on FPGA product, the resistance of the antifuse can be controlled by choosing a sufficiently large programming current level and the resistance remains stable during 1000 h of burn-in at 125 degrees C and 5.75 V. Negligible change in delay time along many different data paths was observed.<>
{"title":"Conductive channel in ONO formed by controlled dielectric breakdown","authors":"S. Chiang, R. Wang, T. Speers, J. Mccollum, E. Hamdy, C. Hu","doi":"10.1109/VLSIT.1992.200623","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200623","url":null,"abstract":"Cross-section TEM photos that capture the conductive channel of oxide-nitride-oxide (ONO) films after electric breakdown are discussed. The photos reveal a single crystal or polycrystal channel with a dome-shaped cap depending on the breakdown current. The implications of this structure for electric characteristics is analyzed with a spherical thermal-electric model. When ONO films are used as antifuse on FPGA product, the resistance of the antifuse can be controlled by choosing a sufficiently large programming current level and the resistance remains stable during 1000 h of burn-in at 125 degrees C and 5.75 V. Negligible change in delay time along many different data paths was observed.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114601942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200627
H. Kyuragi, S. Konaka, T. Kobayashi, K. Deguchi, E. Yamamoto, S. Ohki, Y. Yamamoto
Deep sub-half-micron BiCMOS technology using synchrotron X-ray lithography and two-level metallization featuring planarization and selective CVD Al plugs is described. The process achieves a 0.24- mu m-wide first wiring resist pattern and contact resistivity of 5*10/sup -10/ Omega -cm/sup 2/ for a 0.25- mu m via hole. A 4 K-gate 0.25- mu m CMOS gate array LSI that operates at 58 ps/gate at 2 V was fabricated. This result demonstrates the efficacy of synchrotron X-ray lithography in the fabrication of sub-quarter-micron BiCMOS ULSIs.<>
{"title":"Deep subhalf-micron BiCMOS technology using synchrotron X-ray lithography and its application to 58 ps 2 V CMOS gate array","authors":"H. Kyuragi, S. Konaka, T. Kobayashi, K. Deguchi, E. Yamamoto, S. Ohki, Y. Yamamoto","doi":"10.1109/VLSIT.1992.200627","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200627","url":null,"abstract":"Deep sub-half-micron BiCMOS technology using synchrotron X-ray lithography and two-level metallization featuring planarization and selective CVD Al plugs is described. The process achieves a 0.24- mu m-wide first wiring resist pattern and contact resistivity of 5*10/sup -10/ Omega -cm/sup 2/ for a 0.25- mu m via hole. A 4 K-gate 0.25- mu m CMOS gate array LSI that operates at 58 ps/gate at 2 V was fabricated. This result demonstrates the efficacy of synchrotron X-ray lithography in the fabrication of sub-quarter-micron BiCMOS ULSIs.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128407649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200653
Keh-Jeng Chang, S. Oh, N. Chang, K. Lee
A parameterized interconnect modeling system which provides VLSI designers with a direct link between finite-difference 2-D/3-D capacitance simulators and SPICE simulators is described. In this way, both the device modeling and the interconnect modeling are parameterized, and the time needed to generate SPICE inputs is estimated to decrease by two or three orders of magnitude with this approach.<>
{"title":"Parameterized SPICE subcircuits for submicron multilevel interconnect modeling","authors":"Keh-Jeng Chang, S. Oh, N. Chang, K. Lee","doi":"10.1109/VLSIT.1992.200653","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200653","url":null,"abstract":"A parameterized interconnect modeling system which provides VLSI designers with a direct link between finite-difference 2-D/3-D capacitance simulators and SPICE simulators is described. In this way, both the device modeling and the interconnect modeling are parameterized, and the time needed to generate SPICE inputs is estimated to decrease by two or three orders of magnitude with this approach.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"458 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120879587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200638
S. Koyama
A cell structure using poly Si TFTs (thin film transistors) to realize half-micron channel length, channel width, and isolation space is described. This structure also reduces the drain capacitance relative to conventional structures with cells fabricated on Si substrate with channel doping. A fully-self-aligned polySi TFT cell process sequence without complex SOI technologies such as SIMOX or laser recrystallization is developed. A study of the read-out operation indicates that the application of the TFT cells for EPROMs and flash memories is advantageous not only for access time improvement but also for cell scalability.<>
{"title":"A novel cell structure for giga-bit EPROMs and flash memories using polysilicon thin film transistors","authors":"S. Koyama","doi":"10.1109/VLSIT.1992.200638","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200638","url":null,"abstract":"A cell structure using poly Si TFTs (thin film transistors) to realize half-micron channel length, channel width, and isolation space is described. This structure also reduces the drain capacitance relative to conventional structures with cells fabricated on Si substrate with channel doping. A fully-self-aligned polySi TFT cell process sequence without complex SOI technologies such as SIMOX or laser recrystallization is developed. A study of the read-out operation indicates that the application of the TFT cells for EPROMs and flash memories is advantageous not only for access time improvement but also for cell scalability.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128914011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200635
H. Kuriyama, T. Okada, M. Ashida, O. Sakamoto, K. Yuzuriha, K. Tsutsumi, T. Nishimura, K. Anami, Y. Kohno, H. Miyoshi
A compact SRAM memory cell structure using a set of C-TFTs (complementary thin-film transistors) is discussed. A C-TFT is composed of a top-gate N-channel TFT and a bottom-gate P-channel TFT. The proposed cell's size was reduced to 80% of that of a conventional one at the 16-Mb SRAM level. Also, a stable read operation under a low-supply voltage could be realized by using a C-TFT.<>
{"title":"An asymmetric memory cell using a C-TFT for ULSI SRAMs","authors":"H. Kuriyama, T. Okada, M. Ashida, O. Sakamoto, K. Yuzuriha, K. Tsutsumi, T. Nishimura, K. Anami, Y. Kohno, H. Miyoshi","doi":"10.1109/VLSIT.1992.200635","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200635","url":null,"abstract":"A compact SRAM memory cell structure using a set of C-TFTs (complementary thin-film transistors) is discussed. A C-TFT is composed of a top-gate N-channel TFT and a bottom-gate P-channel TFT. The proposed cell's size was reduced to 80% of that of a conventional one at the 16-Mb SRAM level. Also, a stable read operation under a low-supply voltage could be realized by using a C-TFT.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125902276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200642
P. P. Apte, K. Saraswat
A multiprocessing technology for overcoming the temperature nonuniformity limitations of rapid thermal processing is described. It is shown that the nonuniformity can be corrected by dynamic control of the spatial optical flux profile through two key innovations: (1) a lamp system in which tungsten-halogen point sources are configured in three concentric rings to provide a circularly symmetric flux profile, and (2) multivariable control whereby each of the three rings is independently and dynamically controlled to provide for control over the spatial flux profile. Good temperature uniformity over a wide range of temperatures, pressures, and gas flow rates, thereby adding process flexibility is demonstrated. Implant annealing, oxidation, and CVD of Si have been performed with excellent process uniformity. Multiprocessing has been demonstrated by in situ fabrication of an MOS capacitor.<>
{"title":"Rapid thermal multiprocessing using multivariable control of circularly symmetric 3 zone lamp","authors":"P. P. Apte, K. Saraswat","doi":"10.1109/VLSIT.1992.200642","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200642","url":null,"abstract":"A multiprocessing technology for overcoming the temperature nonuniformity limitations of rapid thermal processing is described. It is shown that the nonuniformity can be corrected by dynamic control of the spatial optical flux profile through two key innovations: (1) a lamp system in which tungsten-halogen point sources are configured in three concentric rings to provide a circularly symmetric flux profile, and (2) multivariable control whereby each of the three rings is independently and dynamically controlled to provide for control over the spatial flux profile. Good temperature uniformity over a wide range of temperatures, pressures, and gas flow rates, thereby adding process flexibility is demonstrated. Implant annealing, oxidation, and CVD of Si have been performed with excellent process uniformity. Multiprocessing has been demonstrated by in situ fabrication of an MOS capacitor.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128750579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-02DOI: 10.1109/VLSIT.1992.200669
J. Cressler, J. Comfort, E. Crabbé, J. Sun, J. Stork
It is shown that a properly designed silicon bipolar technology can achieve significantly faster circuit speed at liquid-nitrogen temperature (LNT) than at room temperature (RT). Transistors were fabricated using a reduced-temperature process employing an in situ doped polysilicon emitter contact, a lightly doped epitaxial emitter cap layer, and a graded SiGe base. The short thermal cycle associated with this emitter contact technology allows the formation of an abrupt, heavily doped base nearly immune to carrier freezeout, while maintaining superior emitter-base leakage characteristics at LNT. Transistors have a current gain ( beta ) as high as 500 at 84 K with a cutoff frequency (f/sub T/) of 61 GHz, up from 43 GHz at 300 K. ECL circuits switch at a record 21.9 ps at 84 K at J/sub cs/=1.0 mA/ mu m/sup 2/ (25.4 ps at 310 K). For completeness the low-temperature properties of this technology are compared with more conventional ipi and pi SiGe-base designs.<>
{"title":"An epitaxial emitter cap, SiGe-base bipolar technology with 22 ps ECL gate delay at liquid nitrogen temperature","authors":"J. Cressler, J. Comfort, E. Crabbé, J. Sun, J. Stork","doi":"10.1109/VLSIT.1992.200669","DOIUrl":"https://doi.org/10.1109/VLSIT.1992.200669","url":null,"abstract":"It is shown that a properly designed silicon bipolar technology can achieve significantly faster circuit speed at liquid-nitrogen temperature (LNT) than at room temperature (RT). Transistors were fabricated using a reduced-temperature process employing an in situ doped polysilicon emitter contact, a lightly doped epitaxial emitter cap layer, and a graded SiGe base. The short thermal cycle associated with this emitter contact technology allows the formation of an abrupt, heavily doped base nearly immune to carrier freezeout, while maintaining superior emitter-base leakage characteristics at LNT. Transistors have a current gain ( beta ) as high as 500 at 84 K with a cutoff frequency (f/sub T/) of 61 GHz, up from 43 GHz at 300 K. ECL circuits switch at a record 21.9 ps at 84 K at J/sub cs/=1.0 mA/ mu m/sup 2/ (25.4 ps at 310 K). For completeness the low-temperature properties of this technology are compared with more conventional ipi and pi SiGe-base designs.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121313404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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