S. Geissler, D. Appenzeller, E. Cohen, S. Charlebois, P. Kartschoke, P. McCormick, N. Rohrer, G. Salem, P. Sandon, B. Singer, T. von Reyn, J. Zimmerman
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引用次数: 27
Abstract
Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are discussed.
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