Pub Date : 2002-11-11DOI: 10.1007/3-540-36135-9_23
Victor Melamed, Harry Stuimer, David Wilkins, Lawrence Chang, K. Normoyle, Sutikshan Bhutani
{"title":"Implementation of a third-generation 1.1GHz 64b microprocessor","authors":"Victor Melamed, Harry Stuimer, David Wilkins, Lawrence Chang, K. Normoyle, Sutikshan Bhutani","doi":"10.1007/3-540-36135-9_23","DOIUrl":"https://doi.org/10.1007/3-540-36135-9_23","url":null,"abstract":"","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122400083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993094
A.T.K. Tang
A 3 /spl mu/V offset op-amp has been designed using both autozeroing and chopping to give 20 nV//spl radic/Hz input noise at DC with low energy at the chopping frequency. The design includes additional circuitry for reduced switching transients. Power consumption is 4 mW from a 5 V supply. Die area is 0.6/spl times/1.12 mm using a 0.6 /spl mu/m double-poly double-metal CMOS process.
{"title":"A 3 /spl mu/V-offset operational amplifier with 20 nV//spl radic/Hz input noise PSD at DC employing both chopping and autozeroing","authors":"A.T.K. Tang","doi":"10.1109/ISSCC.2002.993094","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993094","url":null,"abstract":"A 3 /spl mu/V offset op-amp has been designed using both autozeroing and chopping to give 20 nV//spl radic/Hz input noise at DC with low energy at the chopping frequency. The design includes additional circuitry for reduced switching transients. Power consumption is 4 mW from a 5 V supply. Die area is 0.6/spl times/1.12 mm using a 0.6 /spl mu/m double-poly double-metal CMOS process.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116631503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992938
J. Tierno, A. Rylyakov, S. Rylov, Montek Singh, P. Ampadu, S. Nowick, M. Immediato, S. Gowda
A 6 b 10-tap digital FIR filter has a self-timed datapath, clocked interfaces, and variable latency. The architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. The 0.45 mm/sup 2/ circuit, in 0.18 μm CMOS technology, is operational from 1.2 V to 2.1 V power supply, and has 80 mW dissipation at 300 MSample/s and 4 cycles of latency, and 500 mW at 1.3 GSample/s and 7 cycles of latency.
{"title":"A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces","authors":"J. Tierno, A. Rylyakov, S. Rylov, Montek Singh, P. Ampadu, S. Nowick, M. Immediato, S. Gowda","doi":"10.1109/ISSCC.2002.992938","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992938","url":null,"abstract":"A 6 b 10-tap digital FIR filter has a self-timed datapath, clocked interfaces, and variable latency. The architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. The 0.45 mm/sup 2/ circuit, in 0.18 μm CMOS technology, is operational from 1.2 V to 2.1 V power supply, and has 80 mW dissipation at 300 MSample/s and 4 cycles of latency, and 500 mW at 1.3 GSample/s and 7 cycles of latency.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127447185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992235
J. Lin, B. Haroun
For high-data-rate wireless communication, a 0.8 V 480 /spl mu/W 6b 22 MSample/s flash-interpolation ADC is fabricated in 0.13 /spl mu/m digital CMOS. The circuit achieves 33 dB SNDR and 47 dB SFDR using a nonlinear double-interpolation technique.
{"title":"An embedded 0.8 V/480 /spl mu/W 6b/22 MHz flash ADC in 0.13 /spl mu/m digital CMOS process using nonlinear double-interpolation technique","authors":"J. Lin, B. Haroun","doi":"10.1109/ISSCC.2002.992235","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992235","url":null,"abstract":"For high-data-rate wireless communication, a 0.8 V 480 /spl mu/W 6b 22 MSample/s flash-interpolation ADC is fabricated in 0.13 /spl mu/m digital CMOS. The circuit achieves 33 dB SNDR and 47 dB SFDR using a nonlinear double-interpolation technique.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124699313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992172
H. Kang, H. Kye, Geun-Il Lee, Je-Hoon Park, Jun-Hwan Kim, Seaung-Suk Lee, S. Hong, Young-Jin Park, Jin-Yong Chung
This work develops three concepts: low-voltage operation with boost voltage control of bitline and plateline, reduced bitline capacitance with multiple divided sub cell array, and increased chip performance with write operation sharing both active and precharge time period. A 256 kb test chip with 3.0/spl times/1.0 /spl mu/m/sup 2/ 1T1C memory cells in 0.25 /spl mu/m design roles is expected to achieve 180 ns access and 70 ns precharge at 1.5 V based on internal probing.
{"title":"A hierarchy bitline boost scheme for sub-1.5 V operation and short precharge time on high density FeRAM","authors":"H. Kang, H. Kye, Geun-Il Lee, Je-Hoon Park, Jun-Hwan Kim, Seaung-Suk Lee, S. Hong, Young-Jin Park, Jin-Yong Chung","doi":"10.1109/ISSCC.2002.992172","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992172","url":null,"abstract":"This work develops three concepts: low-voltage operation with boost voltage control of bitline and plateline, reduced bitline capacitance with multiple divided sub cell array, and increased chip performance with write operation sharing both active and precharge time period. A 256 kb test chip with 3.0/spl times/1.0 /spl mu/m/sup 2/ 1T1C memory cells in 0.25 /spl mu/m design roles is expected to achieve 180 ns access and 70 ns precharge at 1.5 V based on internal probing.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124824711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992921
C. Hwang
Information technology (IT) emerged from the 1970s based on main-frame computers. Since then, PCs and the Internet world have drastically expanded the IT industry along with rapid growth of network and communication technology. For almost all platforms, semiconductor memories have been a key enabling technology. In the PC era, DRAM density increase has been driven by rapid expansion of applications with advanced operating systems. In the future, servers will continue driving high-density DRAM requirements, and the maximum memory size of servers will be one of the key performance parameters. 512 Mb DRAM will be widely available in 2002 and 16 Gb DRAM is expected to appear within the next 10 years. Performance of semiconductor memories will be driven by graphics applications and network systems. 1 Gb/s/pin DRAM will be popular in 2002 and 2 Gb/s/pin in 2004 for high-end graphics applications. Random-access times in the range of 5 ns for SRAM and 20 ns for DRAM range and 1 Gb/s/pin DRAM will be available in 2002, and even faster (frequency, latency) memories will be required for high-end network systems such as OC-768-based switches and routers and beyond. Mobile platforms, especially 3 G phones and PDAs, are driving low-voltage low-power memories. Standby power of DRAM and pseudo-SRAM has been reduced drastically over the last 2 years. 1.8 V DRAM will be in volume production in 2002 and 1.0 V DRAM is expected in 2005 for longer battery life and moving-picture capability of mobile applications. The small-form-factor requirement of mobile phones and consumer applications such as PDA, and DSC will expedite various multi-chip-package solutions such as SRAM+Flash, DRAM+Flash, and SRAM+DRAM+Flash. Recent digital convergence and the rapid reduction of $/MB of mass storage flash memory increased the usage of flash memory in various mobile and consumer applications. Semiconductor memory will continue to follow Moore's Law for at least the next 10 years and will be lead by mass storage flash memory technology. Memory requirement of various IT platforms will continue to increase the trend of MB/system and MB/person.
{"title":"Semiconductor memories for IT era","authors":"C. Hwang","doi":"10.1109/ISSCC.2002.992921","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992921","url":null,"abstract":"Information technology (IT) emerged from the 1970s based on main-frame computers. Since then, PCs and the Internet world have drastically expanded the IT industry along with rapid growth of network and communication technology. For almost all platforms, semiconductor memories have been a key enabling technology. In the PC era, DRAM density increase has been driven by rapid expansion of applications with advanced operating systems. In the future, servers will continue driving high-density DRAM requirements, and the maximum memory size of servers will be one of the key performance parameters. 512 Mb DRAM will be widely available in 2002 and 16 Gb DRAM is expected to appear within the next 10 years. Performance of semiconductor memories will be driven by graphics applications and network systems. 1 Gb/s/pin DRAM will be popular in 2002 and 2 Gb/s/pin in 2004 for high-end graphics applications. Random-access times in the range of 5 ns for SRAM and 20 ns for DRAM range and 1 Gb/s/pin DRAM will be available in 2002, and even faster (frequency, latency) memories will be required for high-end network systems such as OC-768-based switches and routers and beyond. Mobile platforms, especially 3 G phones and PDAs, are driving low-voltage low-power memories. Standby power of DRAM and pseudo-SRAM has been reduced drastically over the last 2 years. 1.8 V DRAM will be in volume production in 2002 and 1.0 V DRAM is expected in 2005 for longer battery life and moving-picture capability of mobile applications. The small-form-factor requirement of mobile phones and consumer applications such as PDA, and DSC will expedite various multi-chip-package solutions such as SRAM+Flash, DRAM+Flash, and SRAM+DRAM+Flash. Recent digital convergence and the rapid reduction of $/MB of mass storage flash memory increased the usage of flash memory in various mobile and consumer applications. Semiconductor memory will continue to follow Moore's Law for at least the next 10 years and will be lead by mass storage flash memory technology. Memory requirement of various IT platforms will continue to increase the trend of MB/system and MB/person.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125378918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992958
E. Maayan, R. Dvir, J. Shor, Y. Polansky, Y. Sofer, I. Bloom, D. Avni, B. Eitan, Z. Cohen, M. Meyassed, Y. Alpern, H. Palm, E.S. v Kamienski, P. Haibach, D. Caspary, Sebastian Riedel, R. Knofler
The NROM technology is applied to EEPROM, flash, and data storage product lines. All the products are based on the two-bit-per-cell core technology, using common design concepts, algorithms, circuits, and the same process architecture. Differing product requirements emphasize the versatility of the concept.
{"title":"A 512 Mb NROM flash data storage memory with 8 MB/s data rate","authors":"E. Maayan, R. Dvir, J. Shor, Y. Polansky, Y. Sofer, I. Bloom, D. Avni, B. Eitan, Z. Cohen, M. Meyassed, Y. Alpern, H. Palm, E.S. v Kamienski, P. Haibach, D. Caspary, Sebastian Riedel, R. Knofler","doi":"10.1109/ISSCC.2002.992958","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992958","url":null,"abstract":"The NROM technology is applied to EEPROM, flash, and data storage product lines. All the products are based on the two-bit-per-cell core technology, using common design concepts, algorithms, circuits, and the same process architecture. Differing product requirements emphasize the versatility of the concept.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116015435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993085
H. Nakayama, Toshiyuki Yoshitake, Hiroshi Komazaki, Y. Watanabe, H. Araki, Kiyonori Morioka, Jiang Li, Pei-Yan Liu, Shinhaeng Lee, H. Kubosawa, Y. Otobe
An MPEG-4 video codec core based on a scene-adaptive motion estimation algorithm is integrated into 5.296/spl times/5.296 mm/sup 2/ die using 0.18 /spl mu/m quad-metal technology. The power dissipation during codec operation of the device is 131 mW for QCIF format at 15 frames/s at 13.5 MHz using a 1.5 V supply.
{"title":"An MPEG-4 video LSI with an error-resilient codec core based on a fast motion estimation algorithm","authors":"H. Nakayama, Toshiyuki Yoshitake, Hiroshi Komazaki, Y. Watanabe, H. Araki, Kiyonori Morioka, Jiang Li, Pei-Yan Liu, Shinhaeng Lee, H. Kubosawa, Y. Otobe","doi":"10.1109/ISSCC.2002.993085","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993085","url":null,"abstract":"An MPEG-4 video codec core based on a scene-adaptive motion estimation algorithm is integrated into 5.296/spl times/5.296 mm/sup 2/ die using 0.18 /spl mu/m quad-metal technology. The power dissipation during codec operation of the device is 131 mW for QCIF format at 15 frames/s at 13.5 MHz using a 1.5 V supply.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122122644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993031
H. Noguchi, T. Tateyama, M. Okamoto, H. Uchida, M. Kimura, K. Takahashi
A 9.9-10.8 Gb/s rate adaptive clock and data recovery circuit with 1:16 DMUX are integrated in 0.5 /spl mu/m SiGe BiCMOS. A dual-input voltage-controlled oscillator incorporates a fast and a slow tracking loop with a DC gain enhancer. The chip exhibits 2 mUIrms jitter generation and 0.45 UIpp jitter tolerance in a 4-80 MHz range. Power dissipation is 1.45 W from a 3.3 V supply.
{"title":"A 9.9 G-10.8 Gb/s rate-adaptive clock and data-recovery with no external reference clock for WDM optical fiber transmission","authors":"H. Noguchi, T. Tateyama, M. Okamoto, H. Uchida, M. Kimura, K. Takahashi","doi":"10.1109/ISSCC.2002.993031","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993031","url":null,"abstract":"A 9.9-10.8 Gb/s rate adaptive clock and data recovery circuit with 1:16 DMUX are integrated in 0.5 /spl mu/m SiGe BiCMOS. A dual-input voltage-controlled oscillator incorporates a fast and a slow tracking loop with a DC gain enhancer. The chip exhibits 2 mUIrms jitter generation and 0.45 UIpp jitter tolerance in a 4-80 MHz range. Power dissipation is 1.45 W from a 3.3 V supply.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129537474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993077
Kwang-Hyun Lee, E. Yoon
A 500 dpi capacitive CMOS fingerprint sensor with pixel-level adaptation image enhancement uses virtually-grounded metal shields to suppress parasitic capacitances and capacitive switching networks to generate local threshold level. A 210×100 sensor in 0.6 μm CMOS consumes 40 mW at 5 V supply.
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