{"title":"A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer","authors":"Chan-Hsiang Weng, Tzu-An Wei, Tsung-Hsien Lin","doi":"10.1109/VLSI-DAT.2015.7114517","DOIUrl":null,"url":null,"abstract":"A 3rd-order 3-bit continuous-time delta-sigma modulator incorporating several techniques for performance enhancement is presented. In the quantizer, a proposed 3-bit two-step time-domain quantizer is used to facilitate lower power consumption and smaller chip area. In the loop filter, a single-opamp-biquad technique is adopted to realize a 3rd-order loop filter to reduce the modulator power consumption. With an 8MHz bandwidth and 256-MHz sampling rate, the measured peak SNDR and dynamic range for this 3rd-order modulators are 69.6 and 73 dB, respectively. Fabricated in a 90-nm CMOS, the chip consumes 5.01 mW from 1.2-V/1.6-V supply voltages. The FoM is 127 fJ/conversion.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114517","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 3rd-order 3-bit continuous-time delta-sigma modulator incorporating several techniques for performance enhancement is presented. In the quantizer, a proposed 3-bit two-step time-domain quantizer is used to facilitate lower power consumption and smaller chip area. In the loop filter, a single-opamp-biquad technique is adopted to realize a 3rd-order loop filter to reduce the modulator power consumption. With an 8MHz bandwidth and 256-MHz sampling rate, the measured peak SNDR and dynamic range for this 3rd-order modulators are 69.6 and 73 dB, respectively. Fabricated in a 90-nm CMOS, the chip consumes 5.01 mW from 1.2-V/1.6-V supply voltages. The FoM is 127 fJ/conversion.
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