Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114515
Jiann-Jong Chen, P. Wu, Ta-Wei Chao, Y. Ku, Yuh-Shyan Hwang, Cheng-Chieh Yu
In this paper, a buck converter is designed with a noise-shaping technique to reduce noise and uses synchronous rectification to increase power efficiency. The measured results show the peak noise level less than -84.5dBm at 2MHz and achieve 85% to 93.5% power efficiency with output voltage between 1.8V to 2.5V and a load current range from 50mA to 200mA. The buck converter is fabricated with TSMC 0.35μm CMOS DPQM process. The chip area is 1.417mm*1.239 mm.
{"title":"A low-noise high-efficient buck converter with noise-shaping technique","authors":"Jiann-Jong Chen, P. Wu, Ta-Wei Chao, Y. Ku, Yuh-Shyan Hwang, Cheng-Chieh Yu","doi":"10.1109/VLSI-DAT.2015.7114515","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114515","url":null,"abstract":"In this paper, a buck converter is designed with a noise-shaping technique to reduce noise and uses synchronous rectification to increase power efficiency. The measured results show the peak noise level less than -84.5dBm at 2MHz and achieve 85% to 93.5% power efficiency with output voltage between 1.8V to 2.5V and a load current range from 50mA to 200mA. The buck converter is fabricated with TSMC 0.35μm CMOS DPQM process. The chip area is 1.417mm*1.239 mm.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126635328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114544
Y. Lo
With an aging population, the cost of health care has increased substantially over the years. Today nearly 3 trillion dollars are spent in the United States each year, and it is imperative that we keep the climbing health care expense under control while raising the quality and efficiency of the health care. Point of care is a promising path to meet such goals because it promises timely, personal, and cost effective diagnosis and treatments with improved patient outcomes. However, most of today's point-of-care devices have traded quality and performance for cost and speed. As a result, the clinical utility of today's point-of-care devices has been seriously limited. In this presentation, we will discuss the challenges and potential solutions for new generation biomedical devices and systems for point-of-care applications. These devices will be built upon a lab-on-a-chip platform that integrates many technologies including microfluidics, photonics, nanotechnologies, and electronics. They will also leverage from the prevailing mobile devices for enhanced portability, connectivity, and usability. A few examples of such point-of-care devices for disease diagnosis and health monitoring will be discussed.
{"title":"Biomedical devices and instruments for point-of-care diagnosis","authors":"Y. Lo","doi":"10.1109/VLSI-DAT.2015.7114544","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114544","url":null,"abstract":"With an aging population, the cost of health care has increased substantially over the years. Today nearly 3 trillion dollars are spent in the United States each year, and it is imperative that we keep the climbing health care expense under control while raising the quality and efficiency of the health care. Point of care is a promising path to meet such goals because it promises timely, personal, and cost effective diagnosis and treatments with improved patient outcomes. However, most of today's point-of-care devices have traded quality and performance for cost and speed. As a result, the clinical utility of today's point-of-care devices has been seriously limited. In this presentation, we will discuss the challenges and potential solutions for new generation biomedical devices and systems for point-of-care applications. These devices will be built upon a lab-on-a-chip platform that integrates many technologies including microfluidics, photonics, nanotechnologies, and electronics. They will also leverage from the prevailing mobile devices for enhanced portability, connectivity, and usability. A few examples of such point-of-care devices for disease diagnosis and health monitoring will be discussed.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114901713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114536
Ching-Che Chung, Chi-Tung Chang, Chih-Yu Lin
A high data rate, low-power, and large random jitter tolerance wideband signaling (WBS) transceiver for human body channel communication (BCC) is presented in this paper. Firstly, an investigation of human body channel characteristics from 1MHz to 80MHz is discussed. Then in the transmitter part, the proposed WBS transceiver uses a NRZI encoding scheme to transmit data. At the receiver part, a blind 7X oversampling clock and data recovery (CDR) circuit with the vote mechanism can effectively recover the data which distorted by the frequency drift and random noise from body antenna effects. The proposed WBS transceiver is implemented in a standard performance 90nm CMOS process, and the core area is 0.04 mm2. The supported data rate of the proposed WBS transceiver ranges from 1Mb/s to 40Mb/s. The power consumption is 1.94mW at 40Mb/s, and the bit energy is 0.0485 nJ/b.
{"title":"A 1 Mb/s–40 Mb/s human body channel communication transceiver","authors":"Ching-Che Chung, Chi-Tung Chang, Chih-Yu Lin","doi":"10.1109/VLSI-DAT.2015.7114536","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114536","url":null,"abstract":"A high data rate, low-power, and large random jitter tolerance wideband signaling (WBS) transceiver for human body channel communication (BCC) is presented in this paper. Firstly, an investigation of human body channel characteristics from 1MHz to 80MHz is discussed. Then in the transmitter part, the proposed WBS transceiver uses a NRZI encoding scheme to transmit data. At the receiver part, a blind 7X oversampling clock and data recovery (CDR) circuit with the vote mechanism can effectively recover the data which distorted by the frequency drift and random noise from body antenna effects. The proposed WBS transceiver is implemented in a standard performance 90nm CMOS process, and the core area is 0.04 mm2. The supported data rate of the proposed WBS transceiver ranges from 1Mb/s to 40Mb/s. The power consumption is 1.94mW at 40Mb/s, and the bit energy is 0.0485 nJ/b.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128784130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114567
Mu-lee Huang, C. Hung
A novel approach of constructing an All-Digital Phase Locked Loop (ADPLL) is presented in this paper. A 3-Step symmetric Time-to-Digital Converter (TDC) is proposed with both long dynamic range and high resolution. The Upper-and-Lower-boundaries-Cut-off-Determination (ULCD) logic is presented for a full-custom digital loop filter. With this method, an all-digital PLL can be designed without synthesis procedures. The Digitally-Controlled Oscillator is designed by ring architecture with periodic variation linear. The dynamic range of the TDC is 7.7 ns and the finest resolution of the TDC is only 12.7 ps. System locked time is only 1.62 us. The rms jitter and P-P jitter is 4.68 ps and 38.68 ps in the measurement results. And the power dissipation is only 7.55 mW.
{"title":"Full-custom all-digital phase locked loop for clock generation","authors":"Mu-lee Huang, C. Hung","doi":"10.1109/VLSI-DAT.2015.7114567","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114567","url":null,"abstract":"A novel approach of constructing an All-Digital Phase Locked Loop (ADPLL) is presented in this paper. A 3-Step symmetric Time-to-Digital Converter (TDC) is proposed with both long dynamic range and high resolution. The Upper-and-Lower-boundaries-Cut-off-Determination (ULCD) logic is presented for a full-custom digital loop filter. With this method, an all-digital PLL can be designed without synthesis procedures. The Digitally-Controlled Oscillator is designed by ring architecture with periodic variation linear. The dynamic range of the TDC is 7.7 ns and the finest resolution of the TDC is only 12.7 ps. System locked time is only 1.62 us. The rms jitter and P-P jitter is 4.68 ps and 38.68 ps in the measurement results. And the power dissipation is only 7.55 mW.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126538547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114570
A. Sengupta, Saumya Bhadauria
A novel automated design space exploration (DSE) approach of multi-cycle transient fault detectable datapath based on multi-objective user constraints (power and delay) during high level synthesis (HLS) is presented in this paper. To the best of the authors' knowledge, this is the first work in the literature to solve this problem. The presented approach, driven by bacterial foraging optimization (BFO) algorithm provides easy flexibility to change direction in the design space through tumble/swim actions if a search path is found ineffective. The approach is highly capable of reaching true Pareto optimal region indicated by the closeness of our non-dominated solutions to the true Pareto front and their uniform spreading over the Pareto curve (implying diversity). The contributions of this paper are as follows: a) novel exploration approach for generating high quality transient fault detectable structure based on user provided requirements of power-delay, which is capable of transient error detection; b) novel fault detectable algorithm for handling single and multi-cycle transient faults. The results of the proposed approach indicated an average improvement in Quality of Results (QoR) of >9% and reduction in hardware usage of > 26 % compared to recent approaches that are closer in solving a similar objective.
{"title":"Automated design space exploration of transient fault detectable datapath based on user specified power and delay constraints","authors":"A. Sengupta, Saumya Bhadauria","doi":"10.1109/VLSI-DAT.2015.7114570","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114570","url":null,"abstract":"A novel automated design space exploration (DSE) approach of multi-cycle transient fault detectable datapath based on multi-objective user constraints (power and delay) during high level synthesis (HLS) is presented in this paper. To the best of the authors' knowledge, this is the first work in the literature to solve this problem. The presented approach, driven by bacterial foraging optimization (BFO) algorithm provides easy flexibility to change direction in the design space through tumble/swim actions if a search path is found ineffective. The approach is highly capable of reaching true Pareto optimal region indicated by the closeness of our non-dominated solutions to the true Pareto front and their uniform spreading over the Pareto curve (implying diversity). The contributions of this paper are as follows: a) novel exploration approach for generating high quality transient fault detectable structure based on user provided requirements of power-delay, which is capable of transient error detection; b) novel fault detectable algorithm for handling single and multi-cycle transient faults. The results of the proposed approach indicated an average improvement in Quality of Results (QoR) of >9% and reduction in hardware usage of > 26 % compared to recent approaches that are closer in solving a similar objective.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131433411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114498
Jia-Ju Liao, Shang-Yi Chuang, Chia-Ching Chou, Chia-Chi Chang, W. Fang
This study proposed an effective signal processing system based on Ensemble Empirical Mode Decomposition (EEMD) method for the analysis of Photoplethysmography (PPG). The whole system was implemented on an ARM-based SoC development platform to attain the on-line non-stationary signal processing. A non-invasive near-infrared light sensing device was used to record the continuous PPG as the input signal. According to the non-stationary characteristics of PPG, EEMD is useful to achieve accurate analysis for PPG. The signal was decomposed into several Intrinsic Mode Functions (IMFs) by EEMD. The results showed that the proposed EEMD processor can effectively solve the mode mixing problem of Empirical Mode Decomposition (EMD). This study examined its possibility based on specific architecture with an on-board Xilinx FPGA. It was helpful for non-stationary biomedical signal processing and cardiovascular diseases research.
{"title":"An effective photoplethysmography signal processing system based on EEMD method","authors":"Jia-Ju Liao, Shang-Yi Chuang, Chia-Ching Chou, Chia-Chi Chang, W. Fang","doi":"10.1109/VLSI-DAT.2015.7114498","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114498","url":null,"abstract":"This study proposed an effective signal processing system based on Ensemble Empirical Mode Decomposition (EEMD) method for the analysis of Photoplethysmography (PPG). The whole system was implemented on an ARM-based SoC development platform to attain the on-line non-stationary signal processing. A non-invasive near-infrared light sensing device was used to record the continuous PPG as the input signal. According to the non-stationary characteristics of PPG, EEMD is useful to achieve accurate analysis for PPG. The signal was decomposed into several Intrinsic Mode Functions (IMFs) by EEMD. The results showed that the proposed EEMD processor can effectively solve the mode mixing problem of Empirical Mode Decomposition (EMD). This study examined its possibility based on specific architecture with an on-board Xilinx FPGA. It was helpful for non-stationary biomedical signal processing and cardiovascular diseases research.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124369051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114517
Chan-Hsiang Weng, Tzu-An Wei, Tsung-Hsien Lin
A 3rd-order 3-bit continuous-time delta-sigma modulator incorporating several techniques for performance enhancement is presented. In the quantizer, a proposed 3-bit two-step time-domain quantizer is used to facilitate lower power consumption and smaller chip area. In the loop filter, a single-opamp-biquad technique is adopted to realize a 3rd-order loop filter to reduce the modulator power consumption. With an 8MHz bandwidth and 256-MHz sampling rate, the measured peak SNDR and dynamic range for this 3rd-order modulators are 69.6 and 73 dB, respectively. Fabricated in a 90-nm CMOS, the chip consumes 5.01 mW from 1.2-V/1.6-V supply voltages. The FoM is 127 fJ/conversion.
提出了一种3阶3位连续时间δ - σ调制器，该调制器结合了几种增强性能的技术。在量化器中，为了降低功耗和减小芯片面积，采用了一种建议的3位两步时域量化器。在环路滤波器中，采用单运放大器双路技术实现三阶环路滤波器，以降低调制器功耗。在8MHz带宽和256 mhz采样率下，该三阶调制器的峰值SNDR和动态范围分别为69.6和73 dB。该芯片采用90纳米CMOS制造，在1.2 v /1.6 v电源电压下消耗5.01 mW。FoM为127 fJ/转换。
{"title":"A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer","authors":"Chan-Hsiang Weng, Tzu-An Wei, Tsung-Hsien Lin","doi":"10.1109/VLSI-DAT.2015.7114517","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114517","url":null,"abstract":"A 3rd-order 3-bit continuous-time delta-sigma modulator incorporating several techniques for performance enhancement is presented. In the quantizer, a proposed 3-bit two-step time-domain quantizer is used to facilitate lower power consumption and smaller chip area. In the loop filter, a single-opamp-biquad technique is adopted to realize a 3rd-order loop filter to reduce the modulator power consumption. With an 8MHz bandwidth and 256-MHz sampling rate, the measured peak SNDR and dynamic range for this 3rd-order modulators are 69.6 and 73 dB, respectively. Fabricated in a 90-nm CMOS, the chip consumes 5.01 mW from 1.2-V/1.6-V supply voltages. The FoM is 127 fJ/conversion.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114446492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The traditional LRU replacement policy is susceptible to memory-intensive workloads with large non-reused data like thrashing applications and scan applications. For such workloads, the majority of cache blocks don't get any cache hits during residing in the cache. Cache performance can be improved by reducing the interference from non-reused data. Therefore, the lifetime of other blocks is increased and it can contribute to cache hit. We propose a Lifetime-aware LRU Promotion Policy and show that changing the promotion policy can effective reduce cache miss in the last-level cache. Our promotion policy dynamically adjusts promotion strategy and increases the lifetime for useful cache blocks. The experimental results show that our proposal reduces the average MPKI by 6% and 9% over EAF and DIP, respectively. In multicore, we also improve the performance and reduce the MPKI.
{"title":"Lifetime-aware LRU promotion policy for last-level cache","authors":"Hong-Yi Wu, Chien-Chih Chen, Hsiang-Jen Tsai, Yin-Chi Peng, Tien-Fu Chen","doi":"10.1109/VLSI-DAT.2015.7114579","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114579","url":null,"abstract":"The traditional LRU replacement policy is susceptible to memory-intensive workloads with large non-reused data like thrashing applications and scan applications. For such workloads, the majority of cache blocks don't get any cache hits during residing in the cache. Cache performance can be improved by reducing the interference from non-reused data. Therefore, the lifetime of other blocks is increased and it can contribute to cache hit. We propose a Lifetime-aware LRU Promotion Policy and show that changing the promotion policy can effective reduce cache miss in the last-level cache. Our promotion policy dynamically adjusts promotion strategy and increases the lifetime for useful cache blocks. The experimental results show that our proposal reduces the average MPKI by 6% and 9% over EAF and DIP, respectively. In multicore, we also improve the performance and reduce the MPKI.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124086949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114512
Chih-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, C. Chuang, W. Hwang
For miniaturized multi-gas sensors, the detected multi-gas signals would be self-interfered by responses to multiple gases. In this paper, a fast Independent Component Analysis (FICA) is proposed to restore the original source signals from the mixed signals received by different gas sensors. This FICA is designed and implemented by low power algorithm-architecture co-design considering the tradeoffs among power, delay and accuracy of extracted signals for multi-gas sensor applications. To further reduce the power consumption, a data-length controller is designed to adjust the calculated data-length. Additionally, a stability check unit is utilized to terminate the ICA execution for reduction of the computation time and total energy. Compared with the conventional ICA design, the proposed low-power FICA realizes energy reduction by 75% for multi-gas sensor applications.
{"title":"Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications","authors":"Chih-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, C. Chuang, W. Hwang","doi":"10.1109/VLSI-DAT.2015.7114512","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114512","url":null,"abstract":"For miniaturized multi-gas sensors, the detected multi-gas signals would be self-interfered by responses to multiple gases. In this paper, a fast Independent Component Analysis (FICA) is proposed to restore the original source signals from the mixed signals received by different gas sensors. This FICA is designed and implemented by low power algorithm-architecture co-design considering the tradeoffs among power, delay and accuracy of extracted signals for multi-gas sensor applications. To further reduce the power consumption, a data-length controller is designed to adjust the calculated data-length. Additionally, a stability check unit is utilized to terminate the ICA execution for reduction of the computation time and total energy. Compared with the conventional ICA design, the proposed low-power FICA realizes energy reduction by 75% for multi-gas sensor applications.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125871097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114539
Wei-Lung Yang, Hsi-Pin Ma
In ECG signal processing, we can use discrete wavelet transform (DWT) algorithm to remove unusable features from original signals, and then extract R-R intervals from the reconstructed waveform. In EEG signal processing, we also can use the algorithm based on DWT to observe frequency-domain features in Parkinson's disease (PD). Hence, we proposed a configurable wavelet processor with feature extraction circuit in the sensor for more efficient biomedical applications. We have implemented the design with TSMC 0.18 μm technology. The total core area is 1.15 mm2, the operating voltage is 1.8 V, the operating clock frequency is 360 Hz, and the power consumption is 0.52 μW. Compared with sending raw ECG data, our design saves as much as 99.5% power while only detecting and sending R-R interval sequences in ECG application.
{"title":"A configurable wavelet processor for biomedical applications","authors":"Wei-Lung Yang, Hsi-Pin Ma","doi":"10.1109/VLSI-DAT.2015.7114539","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114539","url":null,"abstract":"In ECG signal processing, we can use discrete wavelet transform (DWT) algorithm to remove unusable features from original signals, and then extract R-R intervals from the reconstructed waveform. In EEG signal processing, we also can use the algorithm based on DWT to observe frequency-domain features in Parkinson's disease (PD). Hence, we proposed a configurable wavelet processor with feature extraction circuit in the sensor for more efficient biomedical applications. We have implemented the design with TSMC 0.18 μm technology. The total core area is 1.15 mm2, the operating voltage is 1.8 V, the operating clock frequency is 360 Hz, and the power consumption is 0.52 μW. Compared with sending raw ECG data, our design saves as much as 99.5% power while only detecting and sending R-R interval sequences in ECG application.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127951450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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