Lithography hotspot detection: From shallow to deep learning

Abstract

As VLSI technology nodes continue, the gap between lithography system manufacturing ability and transistor feature size induces serious problems, thus lithography hotspot detection is of importance in physical verification flow. Existing hotspot detection approaches can be categorized into pattern matching-based and machine learning-based. With extreme scaling of transistor feature size and the growing complexity of layout patterns, the traditional methods may suffer from performance degradation. For example, pattern matching-based methods have lower hotspot detection rates for unseen patterns, while machine learning-based methods may lose information in manual feature extraction for ultra-large-scale integrated circuit masks. To overcome the drawbacks derived from existing methods, in this paper, we survey very recent deep learning techniques and argue that the pooling layers in ordinary deep learning architecture are not necessary. We further propose a novel pooling-free neural network architecture, whose effectiveness is verified by industrial benchmark suites.