{"title":"Practical process flows for monolithic 3D","authors":"Z. Or-Bach","doi":"10.1109/S3S.2013.6716512","DOIUrl":null,"url":null,"abstract":"Three approaches to obtain monolithic 3D logic ICs are presented in this paper. RCAT - Process the high temperature on a generic structure prior to layer transfer (LT), and finish with cold processes; i.e., etch & depositions. Gate Replacement (Gate Last HKMG) - Process the high temperature on a repeating structure prior to LT, and finish with `gate replacement' cold processes. Laser Annealing - Use short laser pulses to locally heat and anneal the top layer while protecting the interconnection layers below from the topside heat. These approaches utilize well-known and manufacturing-friendly materials, process steps and device structures.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2013.6716512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Three approaches to obtain monolithic 3D logic ICs are presented in this paper. RCAT - Process the high temperature on a generic structure prior to layer transfer (LT), and finish with cold processes; i.e., etch & depositions. Gate Replacement (Gate Last HKMG) - Process the high temperature on a repeating structure prior to LT, and finish with `gate replacement' cold processes. Laser Annealing - Use short laser pulses to locally heat and anneal the top layer while protecting the interconnection layers below from the topside heat. These approaches utilize well-known and manufacturing-friendly materials, process steps and device structures.