Pub Date : 2013-10-07DOI: 10.1109/S3S.2013.6716529
C. Márquez, N. Rodriguez, C. Fernandez, A. Ohata, F. Gámiz, F. Allibert, S. Cristoloveanu
Bias Instability is a reliability issue affecting the threshold voltage of a MOS transistor when the gate is stressed with relatively high voltage. For the first time, we characterize the instability of bare SOI wafers using a Pseudo-MOSFET configuration. The effect of positive and negative stress pulses on the properties of both hole and electron channels is systematically investigated. The origins of the instability, the dependence of the degradation with time, and the recovery after the stress have been discussed.dependence
{"title":"Direct point-contact characterization of Bias instability on bare SOI wafers","authors":"C. Márquez, N. Rodriguez, C. Fernandez, A. Ohata, F. Gámiz, F. Allibert, S. Cristoloveanu","doi":"10.1109/S3S.2013.6716529","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716529","url":null,"abstract":"Bias Instability is a reliability issue affecting the threshold voltage of a MOS transistor when the gate is stressed with relatively high voltage. For the first time, we characterize the instability of bare SOI wafers using a Pseudo-MOSFET configuration. The effect of positive and negative stress pulses on the properties of both hole and electron channels is systematically investigated. The origins of the instability, the dependence of the degradation with time, and the recovery after the stress have been discussed.dependence","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132369794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716549
H. Niebojewski, C. Le Royer, Y. Morand, O. Rozeau, M. Jaud, S. Barnola, C. Arvet, J. Pradelles, J. Bustos, J. Pedini, E. Dubois, O. Faynot
We propose an original architecture adapted to the 10nm transistor node (pitch 64nm) for FDSOI technology. This structure features self-aligned contacts and a gate capping dielectric layer preventing any short in case of lithographic misalignment of contacts. 2D simulations are carried out to quantify parasitic capacitances. Technological solutions are then proposed to optimize this key parameter. Consequences are evaluated at the device and circuit scale. It is shown that the use of low-k materials, such as airgap spacers, is a solid option to meet the 10nm node specifications.
{"title":"Self-aligned contacts for 10nm FDSOI Node: From device to circuit evaluation","authors":"H. Niebojewski, C. Le Royer, Y. Morand, O. Rozeau, M. Jaud, S. Barnola, C. Arvet, J. Pradelles, J. Bustos, J. Pedini, E. Dubois, O. Faynot","doi":"10.1109/S3S.2013.6716549","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716549","url":null,"abstract":"We propose an original architecture adapted to the 10nm transistor node (pitch 64nm) for FDSOI technology. This structure features self-aligned contacts and a gate capping dielectric layer preventing any short in case of lithographic misalignment of contacts. 2D simulations are carried out to quantify parasitic capacitances. Technological solutions are then proposed to optimize this key parameter. Consequences are evaluated at the device and circuit scale. It is shown that the use of low-k materials, such as airgap spacers, is a solid option to meet the 10nm node specifications.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115066487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716573
A. Pal, A. Nainani, Z. Ye, X. Bao, E. Sanchez, K. Saraswat
SOI based GaP source drain 1T DRAM with silicon channel is proposed. Using BJT-latch based programing, it is shown that the scalability of GaP-SD 1T-DRAM can be extended up to 20nm. Nickel alloying of GaP is proposed as a method to reduce the sheet and contact resistance of GaP source and drain. Using nickel alloying, the ON-current of the GaP-SD transistor is improved by an order and the proper scalability behavior is established.
{"title":"GaP source-drain SOI 1T-DRAM: Solving the key technological challenges","authors":"A. Pal, A. Nainani, Z. Ye, X. Bao, E. Sanchez, K. Saraswat","doi":"10.1109/S3S.2013.6716573","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716573","url":null,"abstract":"SOI based GaP source drain 1T DRAM with silicon channel is proposed. Using BJT-latch based programing, it is shown that the scalability of GaP-SD 1T-DRAM can be extended up to 20nm. Nickel alloying of GaP is proposed as a method to reduce the sheet and contact resistance of GaP source and drain. Using nickel alloying, the ON-current of the GaP-SD transistor is improved by an order and the proper scalability behavior is established.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122684923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716526
Uldric A. Antao, A. Dibazar, J. Choma, T. Berger
A 12nW sub-threshold event detector with false positive detection has been designed to operate in conjunction with a classifier for an unattended seismic surveillance sensor. 45nW consumed in presence of events. Power is greatly conserved by using the event detector (which never sleeps) to wake up a power consuming microcontroller which performs the classification of the event. The low power seismic sensor has an added circuit to suppress false positives. The proposed work helps alleviate maintenance costs and increases the life time of the sensors. Such ideas can be implemented in other devices where battery life is of crucial importance.
{"title":"Low power false positive tolerant event detector for seismic sensors","authors":"Uldric A. Antao, A. Dibazar, J. Choma, T. Berger","doi":"10.1109/S3S.2013.6716526","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716526","url":null,"abstract":"A 12nW sub-threshold event detector with false positive detection has been designed to operate in conjunction with a classifier for an unattended seismic surveillance sensor. 45nW consumed in presence of events. Power is greatly conserved by using the event detector (which never sleeps) to wake up a power consuming microcontroller which performs the classification of the event. The low power seismic sensor has an added circuit to suppress false positives. The proposed work helps alleviate maintenance costs and increases the life time of the sensors. Such ideas can be implemented in other devices where battery life is of crucial importance.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114400684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716536
V. Joshi, R. Parkhurst, L. Morrell, P. Tornatta
MEMS devices are ideal tuning element since in a non-50 Ohm system, equivalent series resistance (ESR) is the primary source of losses in a tuning system. MEMS have less than 20% of the ESR of solid state devices and are on par with the best fixed-value passive components. Figure 2 shows the usable Q of Cavendish RF MEMS device for the frequency range and associated capacitance state.
{"title":"MEMS Solutions in RF applications","authors":"V. Joshi, R. Parkhurst, L. Morrell, P. Tornatta","doi":"10.1109/S3S.2013.6716536","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716536","url":null,"abstract":"MEMS devices are ideal tuning element since in a non-50 Ohm system, equivalent series resistance (ESR) is the primary source of losses in a tuning system. MEMS have less than 20% of the ESR of solid state devices and are on par with the best fixed-value passive components. Figure 2 shows the usable Q of Cavendish RF MEMS device for the frequency range and associated capacitance state.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130309646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716540
B. Giraud, J. Noel, F. Abouzeid, S. Clerc, Y. Thonnart
The 28nm UTBB FD-SOI design platform enables multi-VT standard cells co-integration with independent back biases (BB). In this paper, we propose a new clock-tree cell to build a robust clock tree isolated from the various BB of the different Vt regions, showing better propagation and transition times balancing (2.5x), and a drastic skew reduction (5x at 0.4V) compared to a conventional clock tree.
{"title":"Robust clock tree using single-well cells for multi-VT 28nm UTBB FD-SOI digital circuits","authors":"B. Giraud, J. Noel, F. Abouzeid, S. Clerc, Y. Thonnart","doi":"10.1109/S3S.2013.6716540","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716540","url":null,"abstract":"The 28nm UTBB FD-SOI design platform enables multi-VT standard cells co-integration with independent back biases (BB). In this paper, we propose a new clock-tree cell to build a robust clock tree isolated from the various BB of the different Vt regions, showing better propagation and transition times balancing (2.5x), and a drastic skew reduction (5x at 0.4V) compared to a conventional clock tree.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115450351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716555
Sebastien Bernard, A. Valentian, M. Belleville, D. Bol, J. Legat
So far, pulse-triggered flip-flops (pulsed-FFs) are mainly used in high-performance digital circuits, thanks to their small data-to-output delay. However, they suffer from a poor robustness to local variations occurring at ultra-low-voltage (ULV). Thanks to an innovative pulse generator, the operability of an energy-efficient pulsed-FF was validated at ultra-low operating supply voltage. Measurements of delays and correct functionality are performed in 28nm FDSOI technology. Then, the effect of back bias voltage, a key point in FDSOI technology, is studied and it is shown that our pulsed-FF reaches a minimum operating supply voltage of 170mV.
{"title":"Design of a robust and ultra-low-voltage pulse-triggered flip-flop in 28nm UTBB-FDSOI technology","authors":"Sebastien Bernard, A. Valentian, M. Belleville, D. Bol, J. Legat","doi":"10.1109/S3S.2013.6716555","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716555","url":null,"abstract":"So far, pulse-triggered flip-flops (pulsed-FFs) are mainly used in high-performance digital circuits, thanks to their small data-to-output delay. However, they suffer from a poor robustness to local variations occurring at ultra-low-voltage (ULV). Thanks to an innovative pulse generator, the operability of an energy-efficient pulsed-FF was validated at ultra-low operating supply voltage. Measurements of delays and correct functionality are performed in 28nm FDSOI technology. Then, the effect of back bias voltage, a key point in FDSOI technology, is studied and it is shown that our pulsed-FF reaches a minimum operating supply voltage of 170mV.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115027078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716514
C. Chen, D. Yost, B. Aull, C. Chen, P. Gouker, J. Knecht, B. Tyrrell, K. Warner, B. Wheeler, P. Wyatt, C. Keast, V. Suntharalingam
Presents a collection of slides covering the following topics: bonding; 3D integrated circuit process flow; lithographic requirements; 3-tier single-photon laser-radar focal plane; Nyquist-limited IR focal planes; CMOS technology and SWIR detectors.
{"title":"3D-enabled heterogeneous integrated circuits","authors":"C. Chen, D. Yost, B. Aull, C. Chen, P. Gouker, J. Knecht, B. Tyrrell, K. Warner, B. Wheeler, P. Wyatt, C. Keast, V. Suntharalingam","doi":"10.1109/S3S.2013.6716514","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716514","url":null,"abstract":"Presents a collection of slides covering the following topics: bonding; 3D integrated circuit process flow; lithographic requirements; 3-tier single-photon laser-radar focal plane; Nyquist-limited IR focal planes; CMOS technology and SWIR detectors.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130274777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716521
A. Paul, C. Yeh, T. Standaert, Jeffrey B. Johnson, A. Bryant, N. Tripathi, G. Tsutsui, T. Yamashita, V. Basker, J. Faltermeier, Jin Cho, H. Bu, M. Khare
This work presents SOI finFETs with fin width (Dfin) scaled to sub 15nm. The process flow provides robust Dfin scaling as depicted by the universal electrostatic scaling of the DIBL and sub-threshold swing (SS). The high field long channel mobility drops by ~6% with Dfin scaling, however, DIBL and SS improves by ~1.5X and ~2X, respectively, for 20nm channel length n/pfinFETs. The effective current (Ieff) at fixed Ioff improves by ~20% and ~30% for p and n finFETs, respectively, with Dfin scaling.
{"title":"Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs","authors":"A. Paul, C. Yeh, T. Standaert, Jeffrey B. Johnson, A. Bryant, N. Tripathi, G. Tsutsui, T. Yamashita, V. Basker, J. Faltermeier, Jin Cho, H. Bu, M. Khare","doi":"10.1109/S3S.2013.6716521","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716521","url":null,"abstract":"This work presents SOI finFETs with fin width (Dfin) scaled to sub 15nm. The process flow provides robust Dfin scaling as depicted by the universal electrostatic scaling of the DIBL and sub-threshold swing (SS). The high field long channel mobility drops by ~6% with Dfin scaling, however, DIBL and SS improves by ~1.5X and ~2X, respectively, for 20nm channel length n/pfinFETs. The effective current (Ieff) at fixed Ioff improves by ~20% and ~30% for p and n finFETs, respectively, with Dfin scaling.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131361577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716575
Zhichao Lu, J. Fossum, D. Sarkar, Zhenming Zhou
Floating-body DRAM cells (FBCs) on SOI are of interest because of integration problems associated with the large storage capacitor of nanoscale conventional 1T/ 1C DRAM. However, limitations on FBC speed, due to relatively slow write times governed by the usual impact-ionization or tunneling body-charging processes, preclude the application of most interest - embedded DRAM. We recently proposed a novel 2T (T1 and T2) FBC, i.e., a floating-body/gate cell (FBGC) , which enables design flexibility for optimizing performance. We present herein a new 2T design concept (FBGC4) that gives ultra-fast write times, in addition to good current-signal margin and long retention times, and thus enables the embedded-DRAM application. Further, low power and good reliability are implied because of low-voltage operation afforded by FBGC4.
{"title":"An ultra-fast floating-body/gate cell for embedded DRAM","authors":"Zhichao Lu, J. Fossum, D. Sarkar, Zhenming Zhou","doi":"10.1109/S3S.2013.6716575","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716575","url":null,"abstract":"Floating-body DRAM cells (FBCs) on SOI are of interest because of integration problems associated with the large storage capacitor of nanoscale conventional 1T/ 1C DRAM. However, limitations on FBC speed, due to relatively slow write times governed by the usual impact-ionization or tunneling body-charging processes, preclude the application of most interest - embedded DRAM. We recently proposed a novel 2T (T1 and T2) FBC, i.e., a floating-body/gate cell (FBGC) , which enables design flexibility for optimizing performance. We present herein a new 2T design concept (FBGC4) that gives ultra-fast write times, in addition to good current-signal margin and long retention times, and thus enables the embedded-DRAM application. Further, low power and good reliability are implied because of low-voltage operation afforded by FBGC4.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131862597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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